Top 468 Design verification engineer Jobs in San Diego, Ca

Principal/ Sr. Principal Digital Verification Engineer
Northrop Grumman —San Diego, CA
- $125,300 - $234,600 a year
- Overtime
- 5 years
- Analysis skills
- Doctor of Philosophy
- Paid holidays
- Disability insurance
Product Security Engineer
Hologic —San Diego, CA
- $109,900 - $171,800 a year
- Full-time
- Computer Science
- Mid-level
- Travel
Staff Engineer Survivability - Software Integration (CA or FL)
Northrop Grumman —San Diego, CA
- $168,200 - $292,100 a year
- Overtime
- Schematics
- Master's degree
- 8 years
- Paid holidays
- Disability insurance
Principal /Sr. Principal Digital Engineer
Northrop Grumman —San Diego, CA
- $125,300 - $234,600 a year
- Overtime
- Bachelor of Science
- Master's degree
- Doctor of Philosophy
- Paid holidays
- Disability insurance
Video Design Verification Engineer
Qualcomm —San Diego, CA
- $99,400 - $149,200 a year
- Computer Science
- Mid-level
- Master's degree
ASICS Design Verification Engineer
Qualcomm —San Diego, CA
- $98,500 - $147,700 a year
- Computer Science
- Engineering
- Mid-level
6d
Design Verification Engineer
Sivaltech —San Diego, CA
- Mid-level
- Electrical Engineering
Power Management Systems Design and Verification Engineer
Qualcomm —San Diego, CA
- $93,200 - $139,800 a year
- Research
- Mid-level
- Master's degree
2d
ASIC Design Verification Engineer (Remote)
Encore Semi, Inc. —San Diego, CA
- $120,000 - $135,000 a year
- Full-time
- Remote
- Computer Science
- Mid-level
- Master's degree
- AD&D insurance
- Paid holidays
6d
Staff Digital Design Engineer
Marvell —San Diego, CA
- $115,200 - $170,390 a year
- Computer Science
- Mid-level
- Master's degree
- Employee stock purchase plan
Analog Mixed-Signal Design Verification Engineer - TeraWave
Blue Origin —San Diego, CA
- $230,398.00 - $322,556.85 a year
- Full-time
- Background check
- 7 years
- DOT physical examination
- Paid parental leave
- Paid holidays
SOC Verification and Methodology Engineer
Qualcomm —San Diego, CA
- $98,500 - $147,700 a year
- Engineering
- Senior level
- 2 years
6d
Front-End Design Engineer
Qualcomm —San Diego, CA
- $115,600 - $173,400 a year
- Engineering
- Mid-level
- Office
ASIC Design Engineer
Career Finders —San Diego, CA
- Mid-level
- Analysis skills
- Electrical Engineering
RTL Design Engineer
Apple —San Diego, CA
- $175,000 - $308,500 a year
- Bachelor of Science
- Data analysis skills
- Analysis skills
- Employee stock purchase plan
- Health insurance
Analog Design Engineer
Elevate Semiconductor —San Diego, CA
- $80,000 - $125,000 a year
- Full-time
- Mid-level
- 3 years
- Master's degree
- Relocation assistance
- Health insurance
Quick Apply
1d
SOC Design Verification Engineer – Data Center Solutions
Qualcomm —San Diego, CA
- $115,600 - $173,400 a year
- Computer Science
- Engineering
- Doctor of Philosophy
RFIC Design Engineer
Qualcomm —San Diego, CA
- $108,400 - $162,600 a year
- Mid-level
- Master's degree
- Analysis skills
14d
PLL IC Design Engineer - TeraWave
Blue Origin —San Diego, CA
- Full-time
- Background check
- 7 years
- DOT physical examination
- Paid parental leave
- Paid holidays
DDR PHY System Design Engineer (San Diego, US)
Qualcomm —San Diego, CA
- $140,000 - $210,000 a year
- Engineering
- System design
- Doctor of Philosophy

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Principal/ Sr. Principal Digital Verification Engineer

Northrop Grumman -
San Diego, CA

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Job Details

$125,300 - $234,600 a year

Benefits

Paid holidays
Disability insurance
Relocation assistance
Health insurance
Paid time off

Qualifications

Requirements specification
Requirements design
FPGA
Electronics test plan development
VHDL
DoD experience
Radio communication systems
Electrical system testing
System design for system development
Telecommunications systems
Electrical engineering training
Design engineering
Schedule creation
Simulation tools
FPGA circuit design
Validation design

Full Job Description

RELOCATION ASSISTANCE: Relocation assistance may be available

CLEARANCE REQUIRED FOR START: Yes

CLEARANCE TYPE: Secret

TRAVEL: Yes, 10% of the Time

Description

At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history.

We are looking for you to join our team as a Principal Digital Verification Engineer or Sr. Principal Digital Verification Engineer based out of San Diego, CA. At the Northrop Grumman San Diego campus our Advanced Digital Design organization creates the next generation of communications and signal processing systems and will take ideas from concept to working systems aboard the world’s most advanced platforms right here in always-sunny San Diego. We design in our campus of labs and on-site advanced manufacturing just minutes from the beach and everything for which southern California is famous. It’s work that matters and a career that can take you places. We seek degreed electrical or computer engineering engineers with hands-on experience in FPGA Verification with VHDL.

You will be responsible for digital designs associated with multi-function software-defined radios. Systems include state-of-art radios and test equipment for military applications.

This is a dual level requisition which can be filled as a Principal Digital Verification Engineer or Sr. Principal Digital Verification Engineer.

This position is contingent upon the ability to obtain a US Government secret clearance and future program awards.

Job Description:

Define and maintain digital logic design verification frameworks and architectures for software-defined radio systems
Develop a verification plan based on digital logic design requirements and design specifications
Simulate and verify FPGA logic designs, requirements, and perform system validation
Analyze and debug simulation failures, determine root causes of bugs, and work with designers to resolve issues
Perform regression testing and generate verification metrics and reporting
Operate in a team environment with 5-7 engineers

Basic Qualifications for a Principal:

Bachelor’s degree in Electrical Engineering or other STEM (Science, Technology, Engineering or Mathematics) discipline
5+ years of digital verification engineering experience using industry standard simulation tools (3+ years with an MS degree; 1+ years with PhD)
Experience in VHDL design and verification methodologies for DoD communications systems
FPGA deployable product process experience (requirements definition, conceptual design, detailed design, verification, and production release)
Experience developing verification plans, functional tests, test benches, and bus functional models
Experience with forecasting and estimating schedules for assigned tasks
Demonstrated strong analytical skills and the ability to prioritize assignments according to program goals
Experience using Siemens Questa Simulator
Must be a US Citizen with the ability to obtain and maintain a Security Clearance

Basic Qualifications for a Sr. Principal:

Bachelor’s degree in Electrical Engineering or other STEM (Science, Technology, Engineering or Mathematics) discipline
8+ years of digital verification engineering experience using industry standard simulation tools (6+ years with an MS degree; 4+ years with PhD)
Experience in VHDL design and verification methodologies for DoD communications systems
FPGA deployable product process experience (requirements definition, conceptual design, detailed design, verification, and production release)
Experience developing verification plans, functional tests, test benches, and bus functional models
Experience with forecasting and estimating schedules for assigned tasks
Demonstrated strong analytical skills and the ability to prioritize assignments according to program goals
Experience using Siemens Questa Simulator
Must be a US Citizen with the ability to obtain and maintain a Security Clearance

Preferred Qualifications:

Active Security Clearance
Experience with functional verification methodology using OSVVM for the full life cycle of products
Experience with scripting languages for Verification automation in a Linux environment (Perl, TCL, Bash, and Makefile)
Experience using Siemens formal applications such as Lint, Inspect, and CDC
Ability to hold special access program clearances

Primary Level Salary Range: $125,300.00 - $187,900.00

Secondary Level Salary Range: $156,400.00 - $234,600.00

The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate's experience, education, skills and current market conditions.

Depending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business.

The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates.

Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO and pay transparency statement, please visit http://www.northropgrumman.com/EEO. U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.

Apply Now

Refine Your Search

design verification engineer jobs in san diego, ca

Principal/ Sr. Principal Digital Verification Engineer

Product Security Engineer

Staff Engineer Survivability - Software Integration (CA or FL)

Principal /Sr. Principal Digital Engineer

Video Design Verification Engineer

ASICS Design Verification Engineer

Design Verification Engineer

Power Management Systems Design and Verification Engineer

ASIC Design Verification Engineer (Remote)

Staff Digital Design Engineer

Analog Mixed-Signal Design Verification Engineer - TeraWave

SOC Verification and Methodology Engineer

Front-End Design Engineer

ASIC Design Engineer

RTL Design Engineer

Analog Design Engineer

SOC Design Verification Engineer – Data Center Solutions

RFIC Design Engineer

PLL IC Design Engineer - TeraWave

DDR PHY System Design Engineer (San Diego, US)

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