Top 582 Design verification engineer Jobs in San Francisco Bay Area, Ca

Design Verification Engineer
OpenAI —San Francisco, CA
- $226,000 - $445,000 a year
- Full-time
- Bachelor of Science
- Mid-level
- 3 years
Infrastructure Verification Engineer
TechBiz Global GmbH —San Francisco, CA
- Full-time
- Remote
- Mid-level
- Analysis skills
- Linux
Quick Apply
Desktop/Workstation Design Engineer
Contact Government Services, LLC —San Francisco, CA
- $116,480 - $158,080 a year
- Full-time
- Hybrid work
- Writing skills
- System design
- Mid-level
- Health insurance
- Dental insurance
Quick Apply
PHY Design Verification Engineer
Apple —San Francisco Bay Area, CA
- $122,700 - $214,300 a year
- Data analysis skills
- Mid-level
- Master's degree
- Employee stock purchase plan
- Health insurance
4d
IC Design Engineer
Lawrence Berkeley National Laboratory —San Francisco Bay Area, CA
- $111,204 - $223,176 a year
- Full-time
- Background check
- No experience needed
- Mid-level
13d
IP Verification Engineer
TechBiz Global GmbH —San Francisco, CA
- Full-time
- Remote
- 5 years
- Senior level
- Electrical Engineering
Quick Apply
Wireless Design Verification Engineer
Apple —San Francisco Bay Area, CA
- $175,000 - $308,500 a year
- 7 years
- Bachelor of Science
- Data analysis skills
- Employee stock purchase plan
- Health insurance
Senior Systems Verification & Validation Engineer
Serve Robotics —San Francisco, CA
- $185,000 - $205,000 a year
- Full-time
- Bachelor of Science
- 8 years
- SQL
System Verification and Validation Engineer
Zoox —Foster City, CA
- $175,000 - $239,000 a year
- Email
- Hybrid work
- 5 years
- Bachelor of Science
- Senior level
- Disability insurance
- Health insurance
Quick Apply
Analog IC Design and Verification Engineer
Neuralink —South San Francisco, CA
- $125,000 - $291,000 a year
- Full-time
- 5 years
- Bachelor of Science
- Master's degree
- Commuter assistance
- Paid holidays
Senior Design Verification Engineer
quadric, Inc —Burlingame, CA
- $110,000 - $270,000 a year
- Full-time
- 5 years
- Office
- Software development
- Health insurance
- Dental insurance
Quick Apply
Principal Engineer - Verification, CI/CD Infrastructure & Embedded Hardware (AISW) - Remote Possible
Qualcomm —San Francisco Bay Area, CA
- $221,600 - $332,400 a year
- Remote
- Computer science
- Computer Science
- Bachelor's degree
1d
Front-End Engineer
Dutch —Oakland, CA
- $90,000 - $120,000 a year
- Hybrid work
- Bachelor's degree
- 1 year
- Senior level
Quick Apply
Design Engineer
Remedy Robotics —San Francisco, CA
- $200,000 - $250,000 a year
- Full-time
- 5 years
- Senior level
- Communication skills
Quick Apply
Analog Mixed-Signal Design Engineer
Epia Neuro —Alameda, CA
- $175,000 - $215,000 a year
- Full-time
- 5 years
- Doctor of Philosophy
- Neurology
- Paid parental leave
- Health insurance
Quick Apply
Senior Harness Design Engineer
Astranis —San Francisco, CA
- $135,000 - $235,000 a year
- 7 years
- Senior level
- Electrical Engineering
Quick Apply
Research Engineer, Chip Design RL (Reinforcement Learning)
Anthropic —San Francisco, CA
- $500,000 - $850,000 a year
- Hybrid work
- Office
- Bachelor's degree
- Experience equivalent to degree accepted
- Parental leave
- Flexible schedule
9d
Design Verification, Forward Deployed Engineering
OpenAI —San Francisco, CA
- $162,000 - $302,000 a year
- Full-time
- 5 years
- Bachelor of Science
- Analysis skills
Frontend Engineer
Loft Orbital Solutions —San Francisco, CA
- $130,000 - $190,000 a year
- Full-time
- No experience needed
- Office
- Entry level
- Paid parental leave
- Health savings account
Electrical Engineer II — Verification & Test
Epia Neuro —Alameda, CA
- $120,000 - $145,000 a year
- Full-time
- Mid-level
- Assembly
- Neurology
- Paid parental leave
- Health insurance
Quick Apply
7d

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Design Verification Engineer

OpenAI -
San Francisco, CA

Apply Now

Job Details

Full-time
$226,000 - $445,000 a year

Qualifications

Regression testing implementation
Defect resolution root cause analysis
Bug Tracking (Quality assurance practices)
Bachelor's degree in electrical engineering
Verification (System development task)
Bachelor of Science
Triage
Electronics test plan development
System architecture
Mid-level
3 years
SoC
Microcontroller programming
Master of Science
Computer Engineering
Master's degree in electrical engineering
Simulation tools
Master's degree in computer science
Engineering functional testing
Test analysis
SystemVerilog
Master's degree in computer engineering
Electrical Engineering
Debugging
Failure analysis

Full Job Description

About the Team:
OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role

OpenAI is developing custom silicon to power the next generation of frontier AI models. We’re looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems—ranging from individual IP blocks to subsystems and full SoC—working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale.

In this role you will:
Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality.

Define verification plans based on architecture and microarchitecture specs.

Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies.

Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness.

Drive bug triage, root cause analysis, and work closely with design teams on resolution.

Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments.

You might thrive in this role if you have:
BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification.

Proven success verifying complex IP or SoC designs in industry-standard flows

Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi).

Strong knowledge of computer architecture concepts, memory and cache systems, coherency, interconnects, and/or ML compute primitives.

Familiarity with performance modeling, formal verification, or emulation is a plus.

Experience working in fast-paced, cross-disciplinary teams with a passion for building reliable hardware.

To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic.

For additional information, please see

OpenAI’s Affirmative Action and Equal Employment Opportunity Policy Statement

.

Background checks for applicants will be administered in accordance with applicable law, and qualified applicants with arrest or conviction records will be considered for employment consistent with those laws, including the San Francisco Fair Chance Ordinance, the Los Angeles County Fair Chance Ordinance for Employers, and the California Fair Chance Act, for US-based candidates. For unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. In addition, job duties require access to secure and protected information technology systems and related data security obligations.

To notify OpenAI that you believe this job posting is non-compliant, please submit a report through

this form

. No response will be provided to inquiries unrelated to job posting compliance.

We are committed to providing reasonable accommodations to applicants with disabilities.

OpenAI Global Applicant Privacy Policy

At OpenAI, we believe artificial intelligence has the potential to help people solve immense global challenges, and we want the upside of AI to be widely shared. Join us in shaping the future of technology.

Compensation

$226K – $445K + Offers Equity

Apply Now

Refine Your Search

design verification engineer jobs in san francisco bay area, ca

Design Verification Engineer

Infrastructure Verification Engineer

Desktop/Workstation Design Engineer

PHY Design Verification Engineer

IC Design Engineer

IP Verification Engineer

Wireless Design Verification Engineer

Senior Systems Verification & Validation Engineer

System Verification and Validation Engineer

Analog IC Design and Verification Engineer

Senior Design Verification Engineer

Principal Engineer - Verification, CI/CD Infrastructure & Embedded Hardware (AISW) - Remote Possible

Front-End Engineer

Design Engineer

Analog Mixed-Signal Design Engineer

Senior Harness Design Engineer

Research Engineer, Chip Design RL (Reinforcement Learning)

Design Verification, Forward Deployed Engineering

Frontend Engineer

Electrical Engineer II — Verification & Test

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