Top 660 Asic design Jobs in San Jose, Ca

Senior ASIC/SoC Physical Design Engineer
Everforth —San Jose, CA
- $150,000 - $250,000 a year
- Full-time
- Master's degree
- Analysis skills
- Mentoring
- Health insurance
- Dental insurance
Quick Apply
10d
ASIC Design Engineer
Sivaltech —Milpitas, CA
- Mid-level
- Bachelor's degree
Jr. Board Design Engineer
Lewiz communications —San Jose, CA
- Mid-level
- Electrical Engineering
ASIC Design Engineer
NVIDIA —Santa Clara, CA
- $116,000 - $218,500 a year
- Full-time
- Computer science
- Computer Science
- Bachelor of Science
ASIC Design Engineer - Neural Engine DMA
Apple —Sunnyvale, CA
- $129,300 - $194,700 a year
- Bachelor's degree
- Entry level
- Under 1 year
- Employee stock purchase plan
- Health insurance
6d
ASIC Design Engineer
Hewlett Packard Enterprise —Sunnyvale, CA
- $120,000 - $243,000 a year
- Full-time
- Office
- Master's degree
- Analysis skills
Design Verification Engineer Graduate (Video Silicon IP) - 2026 Start (BS/MS)
ByteDance —San Jose, CA
- $122,574 - $256,000 a year
- Multiple hires
- Computer Science
- Bachelor of Science
- Fair chance
- Paid parental leave
- Paid holidays
ASIC Design Engineer - New College Grad 2026
NVIDIA —Santa Clara, CA
- $100,000 - $189,750 a year
- Full-time
- Computer science
- Computer Science
- Basic math
8d
Digital Logic + Design Verification Graduate Co-Op Program (US - Fall 2026)
Marvell —Santa Clara, CA
- $35 - $70 an hour
- Full-time
- Office
- Analysis skills
- Electrical Engineering
- Paid holidays
- Health insurance
ASIC DFT Engineer
Cisco Systems —San Jose, CA
- $135,800 - $252,000 a year
- Full-time
- Hybrid work
- 5 years
- Master's degree
- US work authorization
- Paid parental leave
- Paid holidays
ASIC Design Verification Engineer
Cisco Systems —San Jose, CA
- $146,700 - $277,600 a year
- Full-time
- Master's degree
- Bachelor's degree
- Doctor of Philosophy
- Paid parental leave
- Paid holidays
ASIC Design Verification Engineer
Avicena Tech —Sunnyvale, CA
- $0 a year
- Full-time
- Mid-level
- 3 years
- Master's degree
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ASIC Design Engineer Graduate (Video Silicon IP) - 2026 Start (BS/MS)
ByteDance —San Jose, CA
- $122,574 - $256,000 a year
- Multiple hires
- Computer Science
- Bachelor of Science
- Master's degree
- Paid parental leave
- Paid holidays
ASIC Floorplan Design Engineer - New College Grad 2026
NVIDIA —Santa Clara, CA
- $100,000 - $189,750 a year
- Full-time
- Computer science
- Computer Science
- CAD
Digital Design Engineer
Qualcomm —Santa Clara, CA
- $146,711 - $161,200 a year
- Computer Science
- Mid-level
- Master's degree
ASIC Verification Engineer - New College Grad 2026
NVIDIA —Santa Clara, CA
- $100,000 - $189,750 a year
- Full-time
- Computer science
- Computer Science
- Bachelor of Science
10d
ASIC DFT STA Engineer
Cisco Systems —San Jose, CA
- $146,700 - $277,600 a year
- Full-time
- Master's degree
- Analysis skills
- Bachelor's degree
- Paid parental leave
- Paid holidays
ASIC verification Engineer
PTEC Solutions —San Jose, CA
- Mid-level
- 4 years
Principal ASIC Design Engineer
Hewlett Packard Enterprise —Sunnyvale, CA
- $174,000 - $352,500 a year
- Full-time
- Office
- Master's degree
- Analysis skills
ASIC/SoC Design Verification Engineer
TETRAMEM INC —San Jose, CA
- $110,000 - $300,000 a year
- Full-time
- 3 years
- Senior level
- Leadership
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asic design jobs near san jose, ca

Senior ASIC/SoC Physical Design Engineer

Everforth -
San Jose, CA

Quick Apply

Job Details

Full-time
$150,000 - $250,000 a year
10 days ago

Benefits

Health insurance
Dental insurance
401(k)
Paid time off
Vision insurance
Life insurance

Qualifications

Tooling
Semiconductor electronics
SoC
Design engineering

Full Job Description

Senior ASIC/SoC Physical Design Engineer

Job Title: Senior ASIC/SoC Physical Design Engineer
Job Location: San Jose, CA or Irvine, CA
Compensation: $150K - $250K base DOE plus equity
Requirements: ASIC/SoC Physical Design, RTL-to-GDSII, Place and Route (P&R), Static Timing Analysis (STA), Synopsys, FinFET, Power Analysis

Position Overview
We are seeking a highly skilled Senior ASIC/SoC Physical Design Engineer to join our dynamic team. The ideal candidate will play a critical role in advancing our design methodologies and ensuring successful implementation of complex ASIC and SoC designs. You will be responsible for the physical design process, from RTL to GDSII, ensuring optimal performance, power, and area (PPA).

Key Responsibilities

Lead the physical design efforts for ASIC and SoC projects, ensuring high-quality implementations from RTL to GDSII.
Conduct Place and Route (P&R) activities, optimizing for performance, power, and area (PPA).
Perform Static Timing Analysis (STA) to ensure timing closure and meet design specifications.
Utilize Synopsys tools for physical design tasks and maintain up-to-date knowledge of FinFET technology.
Conduct power analysis and implement strategies to minimize power consumption in designs.
Collaborate with cross-functional teams to develop and refine physical design flows and methodologies.
Mentor and guide junior engineers in physical design best practices and tools.

Qualifications

Master's or Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
10+ years of experience in ASIC/SoC physical design roles.
Strong expertise in RTL-to-GDSII flow and physical design methodologies.
Proficient in Place and Route (P&R) and Static Timing Analysis (STA).
Experience with Synopsys EDA tools such as Design Compiler (DC), Fusion Compiler, IC Compiler (ICC2), Primetime etc.
Familiarity with FinFET technology and its implications on physical design.
Solid understanding of power analysis techniques and VLSI physical design principles.

Benefits

Vacation/PTO
Equity
Medical
Dental
Vision
Life Insurance
401k
For this position, you must be currently authorized to work in the United States without the need for sponsorship for a non-immigrant visa. CyberCoders will consider for Employment in the City of Los Angeles qualified Applicants with Criminal Histories in a manner consistent with the requirements of the Los Angeles Fair Chance Initiative for Hiring (Ban the Box) Ordinance.This job was first posted by CyberCoders on 07/18/2026 and applications will be accepted on an ongoing basis until the position is filled or closed.Everforth CyberCoders is proud to be an Equal Opportunity Employer

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, sexual orientation, gender identity or expression, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, status as a crime victim, disability, protected veteran status, or any other characteristic protected by law. Our hiring process includes AI screening for keywords and minimum qualifications, and a virtual recruiter as part of the application process. A human recruiter reviews all results. Click here for details on our virtual recruiter . Everforth CyberCoders will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable state and local law, including but not limited to the Los Angeles County Fair Chance Ordinance, the San Francisco Fair Chance Ordinance, and the California Fair Chance Act. Everforth CyberCoders is committed to working with and providing reasonable accommodation to individuals with physical and mental disabilities. Individuals needing special assistance or an accommodation while seeking employment can contact a member of our Human Resources team at [email protected] to make arrangements.

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