Top 537 Yield engineer Jobs in San Jose Ca

Lead ASIC DFT Engineer
Cyient —San Jose, CA
- $80 - $85 an hour
- Full-time
- Analysis skills
- Mentoring
- In-person
Quick Apply
PCBA Process Engineer
Gorilla Circuits —San Jose, CA
- $90,000 - $120,000 a year
- Full-time
- Engineering
- Mid-level
- 3 years
Quick Apply
11d
Test Engineer
ISE LABS INC AND SUBSIDIARY —San Jose, CA
- $100,000 - $120,000 a year
- Full-time
- Computer Science
- Mid-level
- 3 years
Quick Apply
Optical Manufacturing Engineer
Coherent Corp. —Santa Clara, CA
- $91,625 - $150,000 a year
- Full-time
- English
- Mid-level
- Mentoring
RF Engineer
PASONA N A, INC. —San Jose, CA
- $90,000 - $100,000 a year
- Full-time
- Hybrid work
- Engineering
- Mid-level
- Analysis skills
Product Engineer I
Honeywell Aerospace —San Jose, CA
- Full-time
- Entry level
6d
Staff Process Engineer
Bloom Energy —Fremont, CA
- $114,800 - $165,200 a year
- Weekends as needed
- 5 years
- Bachelor of Science
- Engineering
SMT Process Engineer
PEAK Technical Services Inc. —San Jose, CA
- $80,000 - $95,000 a year
- Microsoft Excel
- CAD
- Mid-level
- Health insurance
- Dental insurance
Quick Apply
Manufacturing Engineer
Everforth —Sunnyvale, CA
- Full-time
- Engineering
- Mid-level
- 3 years
- Health insurance
- Dental insurance
Quick Apply
4d
Test Engineer
Siemens —Fremont, CA
- $109,800 - $197,700 a year
- Full-time
- Hybrid work
- 5 years
- Laboratory experience
- Research
2d
Test Engineer
Texas Instruments —Santa Clara, CA
- $157,000 - $181,500 a year
- Full-time
- Bachelor of Science
- 3 years
- Master's degree
7d
Engineer II - Product
Microchip Technology —San Jose, CA
- $70,304 - $143,000 a year
- Full-time
- Bachelor of Science
- Laboratory experience
- Mid-level
- Employee stock purchase plan
- Health insurance
2d
Associate Industrial Engineer - Semiconductor
Magic Leap —San Jose, CA
- Email
- Bachelor of Science
- Analysis skills
- Bachelor's degree
Quick Apply
9d
MEMS Process and Yield Engineer
SiTime Corporation —Santa Clara, CA
- $98,400 - $135,300 a year
- Full-time
- Bachelor of Science
- Analysis skills
- Doctor of Philosophy
- Health insurance
- Dental insurance
Quick Apply
Manufacturing Engineer, Repair Operations
NVIDIA —Santa Clara, CA
- $200,000 - $322,000 a year
- Full-time
- 5 years
- Bachelor's degree
- Experience equivalent to degree accepted
Manufacturing Integration Engineer
Western Digital —San Jose, CA
- $115,200 - $153,600 a year
- Full-time
- 5 years
- Analysis skills
- Doctor of Philosophy
- Health savings account
- AD&D insurance
Quick Apply
11d
Operations Test Engineer
Apple —Cupertino, CA
- $141,800 - $213,700 a year
- Bachelor of Science
- 3 years
- Analysis skills
- Employee stock purchase plan
- Health insurance
4d
Product Development Engineer
Micron —San Jose, CA
- $145,205 - $193,000 a year
- Full-time
- Computer Science
- Mid-level
- 3 years
- Employee stock purchase plan
- Paid holidays
Principal Product Development Engineer
NVIDIA —Santa Clara, CA
- $240,000 - $379,500 a year
- Full-time
- 11+ years
- Master's degree
- Analysis skills
9d
Manufacturing Engineer II (RF Manufacturing)
Honeywell Aerospace —San Jose, CA
- Full-time
- Mid-level

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yield engineer jobs near san jose ca

Lead ASIC DFT Engineer

Cyient -
San Jose, CA

Quick Apply

Job Details

Full-time | Contract
$80 - $85 an hour

Qualifications

Analog circuit design
Engineering development testing
Electronics functional testing
Integrated circuits (ICs)
Ramps
Analysis skills
SoC
System architecture design
Simulation tools
Root cause analysis
Test analysis
Python
Debugging
Cross-functional communication

Full Job Description

Title - Lead ASIC DFT Engineer

Location – San Jose, CA.

Duration - Contract

Job Description

Experience

10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Key Responsibilities

Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
Act as a technical escalation point for advanced DFT and post-silicon debug issues.
Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

Required Skills & Qualifications

Strong hands-on experience in ASIC DFT with end-to-end ownership.
Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
Experience with MBIST implementation and verification; SMS experience preferred.
Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
Proven post-silicon debug and silicon bring-up experience.
Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
Strong communication skills and the ability to work independently with minimal ramp-up.

Preferred Experience

MBIST post-silicon validation.
ATPG simulations and fault coverage debug.
DFT RTL, DFD, DFT verification, and IP-level DFT integration.
DFT SDC creation and DFT timing closure support.
Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
TCL/PERL scripting for DFT automation, reporting, and debug.
Experience working across multiple ASIC technology nodes and complex product development cycles.
Familiarity with yield learning, diagnosis, and manufacturing test optimization.

Pay: $80.00 - $85.00 per hour

Work Location: In person

Quick Apply

Refine Your Search

yield engineer jobs in san jose ca

Lead ASIC DFT Engineer

PCBA Process Engineer

Test Engineer

Optical Manufacturing Engineer

RF Engineer

Product Engineer I

Staff Process Engineer

SMT Process Engineer

Manufacturing Engineer

Test Engineer

Test Engineer

Engineer II - Product

Associate Industrial Engineer - Semiconductor

MEMS Process and Yield Engineer

Manufacturing Engineer, Repair Operations

Manufacturing Integration Engineer

Operations Test Engineer

Product Development Engineer

Principal Product Development Engineer

Manufacturing Engineer II (RF Manufacturing)

I want to receive the latest job alert for yield engineer in san jose ca

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