Top 813 Failure analysis engineer Jobs in Santa Clara Ca

Lead ASIC DFT Engineer
Cyient —San Jose, CA
- $80 - $85 an hour
- Full-time
- Analysis skills
- Mentoring
- In-person
Quick Apply
Senior Fiber Optic Module Packaging Engineer
Coherent Corp. —Sunnyvale, CA
- $91,625 - $150,000 a year
- Full-time
- Microsoft Outlook
- Computer literacy
- Bachelor of Science
12d
Manufacturing Electrical Engineer
TMP Worldwide India Private Limited for ERS US —Milpitas, CA
- $71,000 - $108,000 a year
- Email
- Engineering
- Mid-level
- Bachelor's degree
- AD&D insurance
- Paid holidays
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Rotating Engineer – Offshore Reliability
Hudson Manpower —Milpitas, CA
- Full-time
- Senior level
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Power Electronics Hardware Engineer
ALTEN Technology USA —Newark, CA
- $120,000 - $140,000 a year
- Full-time
- Engineering
- Pass drug screening
- In-person
- Opportunities for advancement
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Staff Engineer, Failure Analysis Engineering
Analog Devices —San Jose, CA
- $130,168 - $188,490 a year
- Full-time
- 5 years
- Bachelor of Science
- Laboratory experience
- Paid holidays
- Health insurance
23h
Manufacturing Design Engineer (Failure Analysis)
KLA —Milpitas, CA
- $106,700 - $181,400 a year
- Full-time
- Doctoral degree
- Master's degree
- Analysis skills
- Employee stock purchase plan
- Paid holidays
Senior Physical Failure Analysis Engineer
NVIDIA —Santa Clara, CA
- $144,000 - $230,000 a year
- Full-time
- Bachelor of Science
- 8 years
- Assembly
12d
Failure Analysis Engineer
SolarEdge —Milpitas, CA
- Full-time
- Mid-level
- Analysis skills
- Electrical Engineering
Quick Apply
Reliability Integration and Failure Analysis Engineer
Western Digital —San Jose, CA
- $74,900 - $99,800 a year
- Full-time
- Computer Science
- Bachelor of Science
- Analysis skills
- Health savings account
- AD&D insurance
Quick Apply
14d
Member of Technical Staff - Switch Systems Test Engineer
Coherent Corp. —Fremont, CA
- $181,750 - $254,438 a year
- Overtime
- 7 years
- Bachelor of Science
- Travel
12d
Manufacturing Engineer
West Valley Staffing Group —Milpitas, CA
- $90,000 - $150,000 a year
- Customer service
- Mid-level
- Continuous improvement
- Health insurance
- Dental insurance
Quick Apply
SMT Process Engineer
PEAK Technical Services Inc. —San Jose, CA
- $80,000 - $95,000 a year
- Microsoft Excel
- CAD
- Mid-level
- Health insurance
- Dental insurance
Quick Apply
Electrical Test and Product Engineer(jerr)
AppleOne Technical —Sunnyvale, CA
- $70,000 - $100,000 a year
- Full-time
- Mid-level
- US work authorization
- Fair chance
- Health savings account
- Health insurance
Quick Apply
Senior Failure Analysis Engineer, Optical Fault Isolation
NVIDIA —Santa Clara, CA
- $144,000 - $264,500 a year
- Full-time
- 5 years
- Analysis skills
- Senior level
12d
Failure Analysis Engineer
Avicena Tech —Sunnyvale, CA
- Full-time
- Hybrid work
- 5 years
- Bachelor of Science
- Analysis skills
Quick Apply
21h
Hardware Data and Failure Analysis Engineer
Google —Mountain View, CA
- $132,000 - $190,000 a year
- Full-time
- Mid-level
- Master's degree
- SQL
1d
Materials Test Engineer, Failure Analysis
Tesla —Fremont, CA
- $91,600 - $195,600 a year
- Full-time
- Engineering
- Organizational skills
- Senior level
- Commuter assistance
- Health savings account
MicroDisplay Failure Analysis and Return Material Authorization Engineer, Raxium
Google —Fremont, CA
- $159,000 - $231,000 a year
- Full-time
- Computer Science
- Mid-level
- Master's degree
Senior Hardware Validation & Failure Analysis Engineer
Advanced Micro Devices, Inc —Santa Clara, CA
- Analysis skills
- Product management
- Organizational skills

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failure analysis engineer jobs near santa clara ca

Lead ASIC DFT Engineer

Cyient -
San Jose, CA

Quick Apply

Job Details

Full-time | Contract
$80 - $85 an hour

Qualifications

Analog circuit design
Engineering development testing
Electronics functional testing
Integrated circuits (ICs)
Ramps
Analysis skills
SoC
System architecture design
Simulation tools
Root cause analysis
Test analysis
Python
Debugging
Cross-functional communication

Full Job Description

Title - Lead ASIC DFT Engineer

Location – San Jose, CA.

Duration - Contract

Job Description

Experience

10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Key Responsibilities

Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
Act as a technical escalation point for advanced DFT and post-silicon debug issues.
Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

Required Skills & Qualifications

Strong hands-on experience in ASIC DFT with end-to-end ownership.
Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
Experience with MBIST implementation and verification; SMS experience preferred.
Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
Proven post-silicon debug and silicon bring-up experience.
Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
Strong communication skills and the ability to work independently with minimal ramp-up.

Preferred Experience

MBIST post-silicon validation.
ATPG simulations and fault coverage debug.
DFT RTL, DFD, DFT verification, and IP-level DFT integration.
DFT SDC creation and DFT timing closure support.
Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
TCL/PERL scripting for DFT automation, reporting, and debug.
Experience working across multiple ASIC technology nodes and complex product development cycles.
Familiarity with yield learning, diagnosis, and manufacturing test optimization.

Pay: $80.00 - $85.00 per hour

Work Location: In person

Quick Apply

Refine Your Search

failure analysis engineer jobs in santa clara ca

Lead ASIC DFT Engineer

Senior Fiber Optic Module Packaging Engineer

Manufacturing Electrical Engineer

Rotating Engineer – Offshore Reliability

Power Electronics Hardware Engineer

Staff Engineer, Failure Analysis Engineering

Manufacturing Design Engineer (Failure Analysis)

Senior Physical Failure Analysis Engineer

Failure Analysis Engineer

Reliability Integration and Failure Analysis Engineer

Member of Technical Staff - Switch Systems Test Engineer

Manufacturing Engineer

SMT Process Engineer

Electrical Test and Product Engineer(jerr)

Senior Failure Analysis Engineer, Optical Fault Isolation

Failure Analysis Engineer

Hardware Data and Failure Analysis Engineer

Materials Test Engineer, Failure Analysis

MicroDisplay Failure Analysis and Return Material Authorization Engineer, Raxium

Senior Hardware Validation & Failure Analysis Engineer

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