Top 144 Senior design engineer Jobs in Santa Cruz Ca

Senior ASIC Design Engineer – Processor Subsystem
E-Space —Saratoga, CA
- $150,000 - $220,000 a year
- Weekends as needed
- 7 years
- Office
- Master's degree
- Paid holidays
- Paid time off
Senior Principal RFIC Design Engineer
Western Digital —San Jose, CA
- $119,900 - $159,800 a year
- Full-time
- Bachelor of Science
- Bachelor's degree
- Doctor of Philosophy
- Health savings account
- AD&D insurance
Quick Apply
Senior Systems Engineer
E-Space —Saratoga, CA
- $120,000 - $200,000 a year
- Weekends as needed
- Engineering
- Office
- US work authorization
- Paid holidays
- Paid time off
Electronics Design Engineer
Heron Power —Scotts Valley, CA
- $150,000 - $200,000 a year
- Full-time
- 3 years
- Analysis skills
- Manufacturing
Senior DV Engineer
E-Space —Saratoga, CA
- $120,000 - $220,000 a year
- Weekends as needed
- Office
- US work authorization
- Senior level
- Paid holidays
- Paid time off
Sr/Staff Wiring Systems Design Engineer
Joby Aviation —Santa Cruz, CA
- $139,400 - $237,000 a year
- Full-time
- Bachelor of Science
- Senior level
- Electrical Engineering
- Employee stock purchase plan
- Disability insurance
Senior Clinical Development Engineer
Capstan Medical, Inc. —Santa Cruz, CA
- Full-time
- 5 years
- Office
- Analysis skills
- Health insurance
- Dental insurance
Quick Apply
Sr. Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning
Annapurna Labs (U.S.) Inc. —Cupertino, CA
- $183,000 - $247,600 a year
- Full-time
- Bachelor of Science
- Analysis skills
- Doctor of Philosophy
- AD&D insurance
- Health insurance
Product Design Engineer
Apple —Cupertino, CA
- $184,700 - $324,800 a year
- Bachelor of Science
- Analysis skills
- Doctor of Philosophy
- Employee stock purchase plan
- Health insurance
Senior Physical Design Engineer
E-Space —Saratoga, CA
- $120,000 - $220,000 a year
- Weekends as needed
- Office
- 8 years
- Analysis skills
- Paid holidays
- Paid time off
Senior/Staff RF Systems Engineer
Joby Aviation —Santa Cruz, CA
- $139,500 - $234,500 a year
- Full-time
- Management
- Master's degree
- 8 years
- Employee stock purchase plan
- Disability insurance
SENIOR CIVIL ENGINEER
County of Santa Cruz —Santa Cruz, CA
- Online Application
- Office
- Master's degree
- Bachelor's degree
- Paid holidays
- Disability insurance
11d
PMU Silicon Validation Engineer
Apple —Cupertino, CA
- $150,400 - $277,600 a year
- Bachelor of Science
- 3 years
- Analysis skills
- Employee stock purchase plan
- Health insurance
Senior FPGA/DSP Engineer
Joby Aviation —Santa Cruz, CA
- $132,800 - $199,300 a year
- Full-time
- Computer Science
- 5 years
- Doctor of Philosophy
- Employee stock purchase plan
- Disability insurance
Senior Composites Mechanical Engineer
Joby Aviation —Santa Cruz, CA
- $104,800 - $181,000 a year
- Full-time
- 3 years
- Master's degree
- Assembly
- Employee stock purchase plan
- Disability insurance
Senior Autonomy Flight Physics Engineer
Joby Aviation —Santa Cruz, CA
- $164,900 - $225,000 a year
- Full-time
- C++
- Math
- Doctor of Philosophy
- Employee stock purchase plan
- Disability insurance
Staff Flight Research Controls & Navigation Engineer
Joby Aviation —Santa Cruz, CA
- $203,800 - $273,000 a year
- Full-time
- System design
- Analysis skills
- C++
- Employee stock purchase plan
- Disability insurance
Senior Antenna Design Engineer
E-Space —Saratoga, CA
- Weekends as needed
- 7 years
- Master's degree
- Doctor of Philosophy
- Paid holidays
- Paid time off
Senior/Staff Power Electronics Engineer
Heron Power —Scotts Valley, CA
- $120,000 - $200,000 a year
- Full-time
- 3 years
- US work authorization
- Experience equivalent to degree accepted
Loads and Dynamics Engineer
Joby Aviation —Santa Cruz, CA
- $121,500 - $206,100 a year
- Full-time
- Mid-level
- Analysis skills
- Doctor of Philosophy
- Employee stock purchase plan
- Disability insurance

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Senior ASIC Design Engineer – Processor Subsystem

E-Space -
Saratoga, CA

Apply Now

Job Details

Full-time
$150,000 - $220,000 a year

Benefits

Paid holidays
Paid time off

Qualifications

Engineering development testing
Verification (System development task)
Electronics test plan development
SoC
Digital circuit design
Design engineering
System architecture design
Simulation tools
Test Planning (Quality assurance practices)

Full Job Description

Saratoga, CA

E-Space US – Engineering & Operations /

Full-Time /

On-Site

Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place!

E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems.

We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life.

We are seeking a Senior ASIC Design Engineer to join our processor subsystem team, focused on the configuration, integration, and verification planning of Arm processor IP and associated subsystem components for satellite IoT connectivity ASICs. This role sits at the intersection of RTL design and functional verification, requiring a strong grasp of processor subsystem architecture and hands-on experience bringing together complex IP in a cohesive, validated design. We are looking for dedicated self-starters who thrive in a fast-paced environment, can take ownership of complex technical challenges, and drive them through to completion with minimal oversight.

Key Responsibilities:

Configure and integrate Arm processor IP (e.g., Cortex-M series) and associated subsystem components including bus interconnects, memory controllers, and peripheral IP

Define and implement subsystem-level RTL integration, ensuring correct connectivity, clocking, and reset architecture across all subsystem components

Collaborate with SoC architects to translate subsystem requirements into a coherent RTL implementation

Work closely with the verification team to define and develop comprehensive testplans covering subsystem functionality, processor interfaces, and IP integration

Author and review design specifications and integration guides for the processor subsystem

Identify and resolve integration issues across IP boundaries, including protocol, clocking, and reset domain crossings

Support synthesis and timing closure for the processor subsystem in coordination with the physical design team

Participate in design reviews and contribute to continuous improvement of design and integration methodologies

Support bring-up and debug activities for the processor subsystem on post-silicon hardware

Required Qualifications:

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field

7+ years of experience in ASIC/SoC design with a focus on processor subsystem integration

Strong proficiency in RTL design and integration using SystemVerilog or VHDL

Experience working with AMBA bus protocols (AHB, APB, AXI) in the context of subsystem integration

Demonstrated experience collaborating with verification teams on testplan definition and functional coverage

Familiarity with industry-standard EDA tools for RTL compile and simulation (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa)

Familiarity with synthesis flows and static timing analysis in the context of processor subsystems

Preferred Qualifications:

Experience with Arm Corstone or similar processor subsystem reference designs, including hands-on configuration and integration of Arm processor IP (Cortex-M series or similar)

Knowledge of low-power design techniques and their application within processor subsystems

Familiarity with Arm tools such as Socrates, Configuration Wizard, or similar IP configuration tools

Experience with scripting languages (e.g., Python, Tcl, Perl) for design automation and EDA tool flows

Experience with UPF-based power-aware design flows

Background in satellite IoT, embedded communications, or similarly constrained application domains

Experience with post-silicon bring-up and debug of processor subsystems

This is a full time, exempt position, based out of our Saratoga office. The target base pay for this position is $150,000 - $220,000 annually. The total compensation packaged will be determined by various factors such as your relevant job-related knowledge, skills, and experience.

We are redefining how satellites are designed, manufactured and used—so we’re looking for candidates with passion, deep knowledge and direct experience on LEO satellite component development, design and in-orbit activities. If that’s your experience – then we’ll be immediately wow-ed.

E-Space is not currently able to provide employment sponsorship for candidates who do not hold work authorization for the location of this role

Why E-Space is right for you:

As a member of our team, you will play a crucial role in driving our success. Our team members have a strong sense of dedication and responsibility; this includes a strong commitment to our mission to create an entirely new suite of global capabilities to improve lives, business efficiencies and build a smarter planet. This means that there will be times when extra hours, including nights and weekends, may be needed to meet critical deadlines and mission goals. In return, we offer a dynamic work environment with opportunities for professional growth and development and the chance to make a meaningful impact in a high-growth industry.

We want you to make the most of your journey at E-Space. That’s why we support and invest in the physical, emotional and financial well-being of our team members and their families. Some of what you can expect when working at E-Space:

An opportunity to really make a difference
Sustainability at our core
Fair and honest workplace
Innovative thinking is encouraged
Competitive salaries
Continuous learning and development
Health and wellness care options
Financial solutions for the future
Optional legal services (US only)
Paid holidays
Paid time off

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

Apply Now

Refine Your Search

senior design engineer jobs in santa cruz ca

Senior ASIC Design Engineer – Processor Subsystem

Senior Principal RFIC Design Engineer

Senior Systems Engineer

Electronics Design Engineer

Senior DV Engineer

Sr/Staff Wiring Systems Design Engineer

Senior Clinical Development Engineer

Sr. Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning

Product Design Engineer

Senior Physical Design Engineer

Senior/Staff RF Systems Engineer

SENIOR CIVIL ENGINEER

PMU Silicon Validation Engineer

Senior FPGA/DSP Engineer

Senior Composites Mechanical Engineer

Senior Autonomy Flight Physics Engineer

Staff Flight Research Controls & Navigation Engineer

Senior Antenna Design Engineer

Senior/Staff Power Electronics Engineer

Loads and Dynamics Engineer

I want to receive the latest job alert for senior design engineer in santa cruz ca

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