Top 48 Fpga engineer Jobs in Totowa, Nj

Hardware Engineer, FPGA
Normal Computing Corporation —New York, NY
- $200,000 - $400,000 a year
- Full-time
- Hybrid work
- C++
- Senior level
- Python
FPGA Design Engineer
QUANTUM COMPUTING, INC. —Hoboken, NJ
- Bachelor of Science
- System design
- Mid-level
Quick Apply
Senior Systems Security Engineer
BAE Systems Inc. —Totowa, NJ
- $105,827 - $179,906 a year
- Full-time
- 5 years
- Bachelor's degree
- In-person
- Health savings account
- Paid holidays
Sr Specialist, Systems Engineer
L3Harris Technologies —Clifton, NJ
- $106,500 - $197,500 a year
- OSHA
- Presentation skills
- Bachelor's degree
- Paid holidays
- Disability insurance
Director of eSoftware Engineering - FPGA / Equities Low Latency Trading
JPMorganChase —Jersey City, NJ
- $204,250 - $285,000 a year
- Full-time
- 5 years
- Senior level
- Leadership
- Health insurance
- Tuition reimbursement
Linux Engineer - Latency Critical Trading Technology
Millennium Management —New York, NY
- $175,000 - $250,000 a year
- On call
- Computer Science
- System design
- Mid-level
Manufacturing Engineer - Technology
QUANTUM COMPUTING, INC. —Hoboken, NJ
- $90,000 - $108,000 a year
- ERP systems
- Master's degree
- Ability to lift 50 pounds
Quick Apply
Product Manager III
Mercury Systems —Upper Saddle River, NJ
- $75,000 - $177,000 a year
- Full-time
- Hybrid work
- Engineering
- Product management
- Travel
- Employee stock purchase plan
- Paid holidays
Test Engineer II
BAE Systems Inc. —Totowa, NJ
- $86,580 - $147,186 a year
- Full-time
- Hybrid work
- Computer science
- Computer Science
- Mid-level
- Health savings account
- Paid holidays
1d
Software Engineer
Tower Research Capital —New York, NY
- $130,000 - $170,000 a year
- Computer Science
- Mid-level
- 3 years
- Paid time off
- Food provided
C++ Software Engineer
IMC Financial Markets —New York, NY
- $175,000 - $225,000 a year
- Full-time
- Computer Science
- System design
- Mid-level
Senior Principal System Security Lead
BAE Systems Inc. —Totowa, NJ
- $153,377 - $260,743 a year
- Full-time
- Writing skills
- 11+ years
- Bachelor's degree
- Health savings account
- Paid holidays
Embedded Engineer
Distributed Spectrum —New York, NY
- $150,000 - $220,000 a year
- Full-time
- 5 years
- System design
- Office
- Health insurance
- Dental insurance
Firmware Software Engineer
WisEngineering —Dover, NJ
- $65,000 - $130,000 a year
- Writing skills
- Mid-level
- Master's degree
- On-the-job training
Quick Apply
Lead Infrastructure Engineer
JPMorganChase —Jersey City, NJ
- $147,250 - $190,000 a year
- Full-time
- Computer science
- Computer Science
- 5 years
- Health insurance
- Tuition reimbursement
Hardware Engineer, PCB
Normal Computing Corporation —New York, NY
- $200,000 - $400,000 a year
- Full-time
- Hybrid work
- Laboratory experience
- Research
- Senior level
Electrical/Components Engineer
Kearfott —Pine Brook, NJ
- $100,000 - $150,000 a year
- Bachelor of Science
- Writing skills
- Data analysis skills
- Paid holidays
- Disability insurance
Quick Apply
11d
Engineer Software
HII —New York, NY
- $82,000 - $160,000 a year
- Email
- Mid-level
- Master's degree
- Bachelor's degree
- Paid holidays
- Health insurance
Lead Software Engineer - C++, FPGA, Low Latency, Electronic Trading
JPMorganChase —Jersey City, NJ
- $156,750 - $215,000 a year
- Full-time
- Computer Science
- 5 years
- System design
- Health insurance
- Tuition reimbursement
Software Engineer
Peraton —Basking Ridge, NJ
- $112,000 - $179,000 a year
- Computer science
- Azure
- Computer Science
- Health savings account
- Paid holidays
14d

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fpga engineer jobs near totowa, nj

Hardware Engineer, FPGA

Normal Computing Corporation
New York, NY

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Job Details

Full-time
$200,000 - $400,000 a year

Qualifications

AI models
Regression testing implementation
Inter-Integrated Circuit (I2C) protocol
Software engineering
Engineering development testing
Electronics functional testing
Tooling
FPGA
Procurement
Defect analysis
VHDL
Universal asynchronous receiver-transmitter (UART) protocol
Verilog
C++
Docker
Model deployment
Computer hardware
System validation
Serial peripheral interface (SPI) protocol
Oscilloscopes
FPGA circuit design
Root cause analysis
Logic analyzers
Implementing machine learning algorithms
DevOps automation
Senior level
Vivado
Prototypes
GitLab
Python

Full Job Description

About Normal Computing

Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. Conventional chips spend most of their energy forcing determinism onto physics; ours compute with it. Stochastic, in-memory, asynchronous: the result is 10-100× more AI inference per dollar, per watt.

We co-design the full stack: AI-native EDA systems in production with the world's largest semiconductor companies, and the advanced ASICs they make possible. Backed by $85M+ from the world's leading deep-tech investors and built by scientists, engineers, and operators from the labs that built modern computing.

Normal works as one team across New York, Silicon Valley, London, Copenhagen, and Seoul. We hire people who want the hardest version of their craft, across every discipline, at every seniority.

The Role

Validating conventional silicon is a solved discipline. Validating silicon that computes with noise is not, and you will be the one who figures out how. As our FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early software development, and building the test infrastructure for post-silicon bring-up and characterization. Your scope spans the entire FPGA lifecycle: selecting hardware platforms, implementing complex RTL, debugging in the lab, and writing the software that drives it all, working daily with our silicon, EDA, and research teams.

What You Will Own

FPGA Platform Ownership: Lead the selection, procurement, and bring-up of FPGA prototyping platforms (e.g., HAPS, VCU118/VPK180-class boards, or custom hardware) for pre-silicon RTL validation and software development.
RTL Implementation: Adapt and implement complex ASIC RTL onto FPGA targets, including multi-clock-domain architectures, CDC bridges, and timing closure on dense designs.
IP Integration: Integrate in-house designs with third-party and vendor IP; serve as the expert on the AMD/Xilinx ecosystem (Vivado IP Integrator, transceivers, memory controllers).
High-Speed Interfaces: Design, implement, and validate high-speed I/O with a focus on PCIe: our accelerators ship as PCIe cards in standard servers.
Post-Silicon Validation: Build FPGA-based "tester" designs for silicon bring-up, device characterization, and automated test environments.
Hardware-Software Stack: Develop the software layer around the hardware: Python/C++ hardware abstraction, register-map generation, and automated build and regression flows.
Lab Debug: Root-cause complex timing and functional issues in real time using ILA/Vivado Analyzer, oscilloscopes, logic analyzers, and BER/eye-diagram characterization of high-speed links.

What Makes You a Great Fit

Proven industry experience taking FPGA designs from RTL through timing closure to validated hardware, ideally in an ASIC prototyping, emulation, or high-growth hardware environment.
Expert-level SystemVerilog and/or VHDL for synthesis, with deep proficiency in Xilinx Vivado (synthesis, place & route, timing closure, IP catalog).
Hands-on experience implementing and debugging PCIe, plus AXI/AHB, SPI, UART, JTAG, and other common interfaces.
Strong Python for automation, test, and build tooling.
Strong board-level bring-up and lab debugging skills on real hardware.
Startup mindset: you work independently, pivot quickly, and run at ambiguous problems that span hardware, software, and physics.

Bonus Points

Verification frameworks like Cocotb or UVM
Experience deploying ML models to FPGAs (hls4ml, FINN, or custom NN-to-RTL flows), or building real-time, sub-microsecond signal processing pipelines.
Mixed-signal ASIC exposure: digital front-ends, ADC/DAC interfaces, or analog compute.
SERDES tuning and signal integrity fundamentals.
CI/CD for hardware (GitLab CI, Docker-based build and test).

Equal Employment Opportunity Statement

Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.

Accessibility Accommodations

Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at [email protected].

Privacy Notice

By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.

Compensation Range: $200K - $400K

Apply Now

Refine Your Search

fpga engineer jobs in totowa, nj

Hardware Engineer, FPGA

FPGA Design Engineer

Senior Systems Security Engineer

Sr Specialist, Systems Engineer

Director of eSoftware Engineering - FPGA / Equities Low Latency Trading

Linux Engineer - Latency Critical Trading Technology

Manufacturing Engineer - Technology

Product Manager III

Test Engineer II

Software Engineer

C++ Software Engineer

Senior Principal System Security Lead

Embedded Engineer

Firmware Software Engineer

Lead Infrastructure Engineer

Hardware Engineer, PCB

Electrical/Components Engineer

Engineer Software

Lead Software Engineer - C++, FPGA, Low Latency, Electronic Trading

Software Engineer

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About Normal Computing

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What Makes You a Great Fit

Bonus Points

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