Top 78 entry level asic design engineer Jobs

ASIC Digital Design Engineer
General Dynamics Mission Systems, Inc —Annapolis Junction, MD
- $114,489 - $120,750 a year
- Full-time
- Hybrid work
- Mid-level
- Master's degree
- Continuous improvement
FPGA Design Engineer (Level 3 or 4)
Northrop Grumman —Linthicum Heights, MD
- $119,600 - $223,900 a year
- Overtime
- Master's degree
- Bachelor's degree
- Doctor of Philosophy
- Paid holidays
- Disability insurance
Electrical Engineer FPGA/ASIC - Level 3/4 - Dulles
Northrop Grumman —Dulles, VA
- $114,000 - $213,400 a year
- Overtime
- Research
- Master's degree
- Analysis skills
- Paid holidays
- Disability insurance
6d
Principal FPGA/ASIC Engineer - Level 3
Northrop Grumman —Gilbert, AZ
- $79,300 - $147,600 a year
- Overtime
- Research
- Master's degree
- Analysis skills
- Paid holidays
- Disability insurance
Physical Design Engineer
Qualcomm —San Diego, CA
- $98,500 - $147,700 a year
- Computer Science
- Engineering
- Mid-level
9d
Hardware Engineer
Arch Convergence —Concord, MA
- Email
- Entry level
Physical Design Engineer
OpenAI —San Francisco, CA
- $266,000 - $445,000 a year
- Full-time
- Bachelor of Science
- Mid-level
- Bachelor's degree
Design for Test Engineer - Early Career
Marvell —Westborough, MA
- $108,500 - $160,510 a year
- Full-time
- Data analysis skills
- Master's degree
- Analysis skills
- Employee stock purchase plan
SoC ASIC Verification Engineer – New College Grad 2026
NVIDIA —Santa Clara, CA
- $100,000 - $189,750 a year
- Full-time
- Computer Science
- Master's degree
- Analysis skills
ASIC Clocks Verification Engineer - New College Grad 2026
NVIDIA —Santa Clara, CA
- $116,000 - $218,500 a year
- Full-time
- Hybrid work
- Mid-level
- Master's degree
- Experience equivalent to degree accepted
Power Architect - New College Grad 2026
NVIDIA —Austin, TX
- $116,000 - $218,500 a year
- Full-time
- Doctor of Philosophy
- Electrical Engineering
- Entry level
SoC Digital Design Engineer, Multimedia Lab
TikTok —San Jose, CA
- $156,000 - $316,800 a year
- Computer Science
- Mid-level
- Analysis skills
- Paid parental leave
- Paid holidays
ASIC Hardware Design Engineer - New College Grad 2026
NVIDIA —Austin, TX
- $116,000 - $218,500 a year
- Full-time
- Master's degree
- Analysis skills
- Software development
Design Engineer
Innogrit —San Jose, CA
- Full-time
- Computer science
- Computer Science
- Master's degree
Quick Apply
Electrical Engineer
Valve Software —Bellevue, WA
- Mid-level
- Experience equivalent to degree accepted
- Electrical Engineering
- Health insurance
- Adoption assistance
ASIC Design Verification Engineer
Cisco Systems —San Jose, CA
- $146,700 - $277,600 a year
- Full-time
- Master's degree
- Bachelor's degree
- Doctor of Philosophy
- Paid parental leave
- Paid holidays
Cell Modeling and Verification Engineer - New College Grad 2026
NVIDIA —Santa Clara, CA
- $100,000 - $189,750 a year
- Full-time
- Mid-level
- Master's degree
- Electrical Engineering
Modem HW Design Engineer – AI Driven Next Gen Modem Hardware Development
Qualcomm —Santa Clara, CA
- $104,000 - $191,900 a year
- Computer Science
- Mid-level
- Master's degree
ASIC Design Verification Emulation Engineer
Cisco Systems —San Jose, CA
- $146,700 - $277,600 a year
- Full-time
- Master's degree
- Bachelor's degree
- Doctor of Philosophy
- Paid parental leave
- Paid holidays
SoC Digital Verification Engineer, Multimedia Lab
TikTok —San Jose, CA
- $156,000 - $316,800 a year
- Computer Science
- Mid-level
- Analysis skills
- Paid parental leave
- Paid holidays

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ASIC Digital Design Engineer

General Dynamics Mission Systems, Inc -
Annapolis Junction, MD

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Job Details

Full-time
$114,489 - $120,750 a year

Qualifications

Application Integration
AI use case identification
Systems integration
Bachelor's degree in electrical engineering
FPGA
System performance optimization
VHDL
Test-driven development
Mid-level
Electronics design
Master's degree
Verilog
Bachelor’s degree in engineering
Continuous improvement
Design engineering
Computer Engineering
Product design
Engineering product development
FPGA circuit design
Bachelor's degree in mathematics
Electrical Engineering
Electrical optimization
Under 1 year

Full Job Description

Basic Qualifications :

Education Requirements:

Requires a Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology or Mathematics field. Also requires 2+ years of job-related experience, or a Master's degree and 6 months of job-related experience.

Clearance Requirements:

Ability to obtain a Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.

Responsibilities for this Position:

ROLE AND POSITION OBJECTIVES:

What You’ll Get to Do:

Collaborate with team leaders to explore and clearly identify real problems and solutions.
Refine and improve the microarchitecture of the IP to optimize performance, I/O, power consumption, area utilization, recurring cost and security functions.
Implement and simulate IP blocks in RTL using SystemVerilog, VHDL, and other languages.
Integrate complex systems that instantiate both the organization's and third party IP.
Contribute to all aspects of design success from specification to production.
Apply our state-of-the-art IP to ASIC and FPGA products in the real world.
Use high-quality design methods and processes to achieve excellent results.

Knowledge, Skills and Abilities:

Solid technical understanding of FPGA or ASIC product development
Experience with SystemVerilog, VHDL, and Test-Driven Development principles
Ability to communicate clearly in person and in written documentation
Degree in Computer Engineering, Computer Science, Electrical Engineering or related field
Identifies opportunities to apply AI for continuous improvement and innovation

#LI-Hybrid

Salary Note: This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled. Combined Salary Range: USD $114,489.00 - USD $120,750.00 /Yr. Company Overview:

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!

Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans

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Refine Your Search

entry level asic design engineer jobs

ASIC Digital Design Engineer

FPGA Design Engineer (Level 3 or 4)

Electrical Engineer FPGA/ASIC - Level 3/4 - Dulles

Principal FPGA/ASIC Engineer - Level 3

Physical Design Engineer

Hardware Engineer

Physical Design Engineer

Design for Test Engineer - Early Career

SoC ASIC Verification Engineer – New College Grad 2026

ASIC Clocks Verification Engineer - New College Grad 2026

Power Architect - New College Grad 2026

SoC Digital Design Engineer, Multimedia Lab

ASIC Hardware Design Engineer - New College Grad 2026

Design Engineer

Electrical Engineer

ASIC Design Verification Engineer

Cell Modeling and Verification Engineer - New College Grad 2026

Modem HW Design Engineer – AI Driven Next Gen Modem Hardware Development

ASIC Design Verification Emulation Engineer

SoC Digital Verification Engineer, Multimedia Lab

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