Top 1277 Dft engineer Jobs

Lead ASIC DFT Engineer
Cyient —Remote
- From $100 an hour
- Full-time
- Remote
- Analysis skills
- Mentoring
- Senior level
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DFT Engineer
Delos Data Inc —Palo Alto, CA
- $160,000 - $220,000 a year
- Full-time
- Remote
- 5 years
- Master's degree
- Analysis skills
- 401(k)
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DFT Engineer - New College Grad
NVIDIA —Santa Clara, CA
- $116,000 - $218,500 a year
- Full-time
- CAD
- Analysis skills
- Mentoring
Test Engineer
Schweitzer Engineering Laboratories, Inc. —Pullman, WA
- $84,200 - $170,400 a year
- Full-time
- Bachelor of Science
- Mid-level
- Residential
- Tuition reimbursement
- Employee stock ownership plan
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Test and Automation Engineer
Safran —Sarasota, FL
- Full-time
- Office
- 3 years
- Programmable logic controllers
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9d
Field Engineer
Digital Force Technologies —San Diego, CA
- $85,000 - $125,000 a year
- Full-time
- Up to 50% travel
- Military
- Mid-level
- Health savings account
- Disability insurance
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Test Engineer
Schweitzer Engineering Laboratories, Inc. —Lewiston, ID
- $84,200 - $170,400 a year
- Full-time
- Bachelor of Science
- Mid-level
- Residential
- Tuition reimbursement
- Employee stock ownership plan
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Sr. Hardware Engineer-North Carolina
Allied Telesis —Cary, NC
- $110,000 - $130,000 a year
- Full-time
- 6 years
- Research
- Mentoring
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Senior Electrical Engineer
Optical Zonu Corp. —Van Nuys, CA
- $100,000 - $175,000 a year
- Full-time
- Laboratory experience
- Analysis skills
- Continuous improvement
- Health insurance
- Dental insurance
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3d
Engines Manufacturing Engineer- (All Levels/All Shifts)
Blue Origin —Huntsville, AL
- Extended hours
- Background check
- Bachelor of Science
- DOT physical examination
- Paid parental leave
- Paid holidays
Electrical Test Engineer
Excelion Partners —Minneapolis, MN
- $110,000 - $130,000 a year
- Full-time
- 5 years
- Bachelor of Science
- Mentoring
- Relocation assistance
- Health insurance
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Process Engineer (SMT/PCA)
VM Services, Inc. (member of the Venture Group of Companies) —Milpitas, CA
- $97,000 - $112,000 a year
- Full-time
- 5 years
- Master's degree
- Bachelor's degree
- Health insurance
- Dental insurance
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Hardware Test and Validation Engineer
Capgemini —San Francisco, CA
- $53,580 - $150,000 a year
- Full-time
- Bachelor of Science
- Experience equivalent to degree accepted
- In-person
- Paid holidays
- Disability insurance
Senior Analog/Mixed-Signal Hardware Engineer
AFEX Fire Suppression Systems —Raleigh, NC
- $80,000 - $130,000 a year
- Full-time
- 5 years
- Analysis skills
- In-person
- Health savings account
- Health insurance
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2d
Staff Verification Design Engineer, DRAM
Micron —Boise, ID
- 5 years
- Mentoring
- In-person
- Paid holidays
- Health insurance
RF Test Development Engineer
Celestica —Maple Grove, MN
- $118,000 - $150,000 a year
- Full-time
- 7 years
- System design
- Office
- Disability insurance
- Health insurance
Senior Test Technician
Digital Force Technologies —San Diego, CA
- $38 - $45 an hour
- Full-time
- Background check
- Microsoft Excel
- Analysis skills
- Paid training
- Health savings account
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Lead ASIC DFT Engineer
Cyient —San Jose, CA
- $80 - $85 an hour
- Full-time
- Analysis skills
- Mentoring
- In-person
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Electrical Assembler
Digital Force Technologies —San Diego, CA
- $30 - $36 an hour
- Full-time
- Microsoft Excel
- Microsoft Outlook
- ERP systems
- Health savings account
- Disability insurance
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Sr. Electrical Engineer @ IoT Startup
Level Home —Redwood City, CA
- $140,000 - $220,000 a year
- 8 hour shift
- Background check
- Assembly
- Mentoring
- Relocation assistance
- Health insurance
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Lead ASIC DFT Engineer

Cyient -
Remote

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Job Details

Full-time | Contract
From $100 an hour

Qualifications

Engineering development testing
Electronics functional testing
Integrated circuits (ICs)
Analysis skills
SoC
Digital circuit design
Product development
System architecture design
Simulation tools
Test analysis
Python
Debugging
Cross-functional communication

Full Job Description

Experience

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Key Responsibilities

Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
Act as a technical escalation point for advanced DFT and post-silicon debug issues.
Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

Required Skills & Qualifications

Strong hands-on experience in ASIC DFT with end-to-end ownership.
Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
Experience with MBIST implementation and verification; SMS experience preferred.
Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
Proven post-silicon debug and silicon bring-up experience.
Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
Strong communication skills and the ability to work independently with minimal ramp-up.

Preferred Experience

MBIST post-silicon validation.
ATPG simulations and fault coverage debug.
DFT RTL, DFD, DFT verification, and IP-level DFT integration.
DFT SDC creation and DFT timing closure support.
Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
TCL/PERL scripting for DFT automation, reporting, and debug.
Experience working across multiple ASIC technology nodes and complex product development cycles.
Familiarity with yield learning, diagnosis, and manufacturing test optimization.

Pay: From $100.00 per hour

Work Location: Remote

Quick Apply

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dft engineer jobs

Lead ASIC DFT Engineer

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Lead ASIC DFT Engineer

Electrical Assembler

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