Asic Designer Salaries in Mountain View, CA

Hands on experience in all aspects of the chip development process with proficiency in front end tools and methodologies. Integrate complex IPs into the SOC.

11 days ago

You will own RTL from microarchitecture to tapeout: writing microarchitecture specifications, creating synthesizable SystemVerilog, working with design…

$200,000 - $400,000 a year

Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB), and methodologies (UVM or equivalent).

$116,000 - $218,500 a year

Strong in micro-architecture and RTL development (Verilog), as well as entire front-end flows including logic synthesis, power, and timing analysis.

$116,000 - $218,500 a year

Develop the verification infrastructure using state of the art verification methodologies and tools. You are encouraged to understand the design and its…

$100,000 - $189,750 a year

5 days ago

Across the full front-end design cycle. State machines, pipelining, parallelism, and timing. Collaborating with fellow designers and architecture teams to…

$129,300 - $194,700 a year