Top 146 Fpga engineer Jobs in Columbia Md

Senior ASIC Digital Design Engineer
General Dynamics Mission Systems, Inc —Annapolis Junction, MD
- $142,166 - $150,000 a year
- Full-time
- Remote
- 3 years
- Master's degree
- Analysis skills
Sensor and Detector Design Engineer
Johns Hopkins Applied Physics Laboratory (APL) —Laurel, MD
- $100,000 - $245,000 a year
- Full-time
- Mid-level
- Master's degree
- Analysis skills
- Disability insurance
- Health insurance
12d
Engineer/Developer - Software, Hardware, Research (Capabilities Development Specialist)
National Security Agency —Fort Meade, MD
- $105,262 - $197,200 a year
- 8 hour shift
- Doctoral degree
- Computer Science
- System design
3d
Senior ASIC Physical Design Engineer
Johns Hopkins Applied Physics Laboratory (APL) —Laurel, MD
- $105,000 - $290,000 a year
- Full-time
- 6 years
- Continuous improvement
- Scripting
- Disability insurance
- Health insurance
12d
FPGA Design Engineer Level 2
Northrop Grumman —Linthicum Heights, MD
- $96,300 - $144,500 a year
- Overtime
- Mid-level
- Master's degree
- Analysis skills
- Paid holidays
- Disability insurance
12d
Lead ASIC Digital Design Engineer
General Dynamics Mission Systems, Inc —Annapolis Junction, MD
- $176,512 - $187,000 a year
- Full-time
- Remote
- 6 years
- Master's degree
- Analysis skills
FPGA Verification Engineer Level 3/4 - Linthicum
Northrop Grumman —Linthicum Heights, MD
- $119,600 - $223,900 a year
- Overtime
- Computer science
- Computer Science
- Master's degree
- Paid holidays
- Disability insurance
Digital Design Engineer - Level 5 - Linthicum
Northrop Grumman —Linthicum Heights, MD
- $185,900 - $278,900 a year
- Overtime
- Computer science
- 7 years
- Computer Science
- Paid holidays
- Disability insurance
FPGA Engineer (part-time)
Interclypse, Inc. —Annapolis Junction, MD
- Part-time
- Mid-level
- Electrical Engineering
FPGA Verification Engineer, Bespoke Solutions
Amazon Development Center U.S., Inc. —Jessup, MD
- $136,000 - $184,000 a year
- Full-time
- Office
- Continuous improvement
- Senior level
- AD&D insurance
- Health insurance
FPGA / Reverse Software Engineer
GIGATEC —Annapolis Junction, MD
- $126,000 - $235,000 a year
- Full-time
- Software troubleshooting
- System design
- Mid-level
- Paid holidays
- Loan repayment program
Quick Apply
Hardware Engineer (High Performance Computing Digital Design Engineering) - Entry Level (Maryland)
US National Security Agency/Central Security Service —Fort Meade, MD
- $87,362 - $123,388 a year
- 8 hour shift
- Hybrid work
- Background check
- Computer Science
- Customer service
2d
Junior FPGA Design Engineer
Carr Astronautics Corporation —Greenbelt, MD
- Computer science
- Computer Science
- Bachelor of Science
Hardware Engineer (High Performance Computing Digital Design Engineering)
National Security Agency —Fort Meade, MD
- $87,362 - $123,388 a year
- 8 hour shift
- Computer Science
- No experience needed
- Mid-level
3d
FPGA Engineer
PLEX Solutions, LLC —Annapolis Junction, MD
- $120,000 - $165,000 a year
- Online Application
- Computer science
- Computer Science
- Bachelor of Science
- Profit sharing
- Health insurance
Quick Apply
Software Engineer (FPGA, Ghidra)-All Levels
Legato, LLC —Annapolis Junction, MD
- $120,000 - $240,000 a year
- Full-time
- Computer Science
- Bachelor of Science
- 11+ years
- Health insurance
- Dental insurance
Quick Apply
Principal FPGA Engineer
Thales —Clarksburg, MD
- $164,452 - $210,133 a year
- Hybrid work
- 6 years
- Bachelor of Science
- System design
- Paid parental leave
- Paid holidays
Software Engineer 0
InterImage —Fort Meade, MD
- $62,000 - $92,000 a year
- Full-time
- Bachelor of Science
- Windows
- Java
- Profit sharing
- Health insurance
Quick Apply
2026 Graduate - Mechanical Engineer - Space Science Instrumentation
Johns Hopkins Applied Physics Laboratory (APL) —Laurel, MD
- $85,000 - $165,000 a year
- Full-time
- Master's degree
- Analysis skills
- Travel
- Disability insurance
- Health insurance
Software Engineer (Ghidra/FPGA) 2026-0146
Acclaim Technical Services —Annapolis Junction, MD
- $270,000 a year
- Full-time
- Computer Science
- System design
- Senior level
- Health insurance
- Employee stock ownership plan
Quick Apply

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fpga engineer jobs near columbia md

Senior ASIC Digital Design Engineer

General Dynamics Mission Systems, Inc -
Annapolis Junction, MD

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Job Details

Full-time
$142,166 - $150,000 a year

Qualifications

Jira
Defect resolution root cause analysis
Bug Tracking (Quality assurance practices)
Engineering development testing
Bachelor's degree in electrical engineering
Verification (System development task)
FPGA
Triage
Electrical engineering
Electronics design
3 years
Master's degree
Collaboration with product development teams
Analysis skills
Documentation tools
Bachelor's degree in engineering
Issue tracking
Design engineering
Computer Engineering
Digital project management boards
Cost estimate preparation
Cost estimates
Test Execution (Quality assurance practices)
Simulation tools
Productivity software
FPGA circuit design
Defect tracking tools
Senior level
Electrical Engineering
Communication skills

Full Job Description

Basic Qualifications :

Education Requirements:

Requires a Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology or Mathematics field. Also requires 5+ years of job-related experience, or a Master's degree plus 3 years of job-related experience.

Clearance Requirements:

Ability to obtain a Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.

Responsibilities for this Position:

We're looking for an Advanced ASIC Design Engineer with solid hands-on experience in RTL design and a foundational understanding of the full ASIC/FPGA design lifecycle. This is a technical role for someone who is ready to take on meaningful ownership of design tasks within a collaborative, high-performing team.

If your career has been primarily running P&R tools, this probably isn't the right fit. We also need someone who has moved beyond the "burn it and see if it works" model of FPGA development — on ASIC, you don't get that luxury. We need an RTL designer who understands that correctness has to be established through rigorous simulation, formal verification, and independent review long before anything gets near silicon.

The right candidate has worked in larger, structured design environments where verification is a discipline in its own right — with dedicated verification partners, formal review processes, and clear functional closure criteria. A self-starter who can work independently on assigned tasks, drives progress without constant direction, and brings a problem-solving mindset to everything they touch.

What You'll Do

Own RTL design tasks — Develop RTL with a focus on correctness: bus fabric integrity, clock domain crossings, reset order-of-operations, and design-for-verification
Contribute to timing closure — Work through synthesis, place and route, and static timing analysis; identify root causes of timing failures and contribute to fixes
Support verification efforts — Execute test and simulation plans in coordination with a dedicated verification team; understand and work within a formal verification process; verify results and help drive closure on failures
Participate in JIRA triage — Review incoming issues and help maintain an accurate and actionable backlog
Participate in code reviews — Engage in RTL code reviews, providing and receiving constructive technical feedback
Support program planning — Provide input on task status, schedule risk, and level of effort to support IMS and EV reporting
Support proposals — Contribute to basis of estimates (BOEs) for proposals, providing technical input on scope and level of effort for assigned design tasks
Support technology evaluation — Assist in assessing foundry technologies, device libraries, IP cores, and EDA tooling
Collaborate broadly — Participate in Integrated Product Teams and working groups

What We're Looking For

5–8+ years of ASIC/FPGA design experience, with meaningful time spent as an RTL designer
Experience working in larger, structured design teams with formal verification processes and independent verification partners — not solely in small-team or solo development environments
Demonstrated understanding that design correctness is established through simulation, formal verification, and peer review — not through iteration on hardware
Some experience contributing to ASIC tape-out efforts is a plus
Familiarity with FinFET process nodes (7nm, 5nm, or similar) is a differentiator
Familiarity with commercial foundry flows (TSMC, GlobalFoundries, Samsung, or equivalent)
Working knowledge of:
RTL design and microarchitecture
Bus fabric design and verification
Clock domain crossing (CDC) analysis
Reset sequencing and validation
Timing closure fundamentals
Power analysis basics

Skills & Knowledge

Solid understanding of ASIC/FPGA engineering concepts, RTL coding practices, and synthesis flows
Familiarity with industry-standard EDA tools (synthesis, simulation, formal verification, STA)
Ability to work independently on assigned tasks while coordinating effectively within the team
Familiarity with vendor and foundry capabilities
Proficiency in JIRA for issue tracking and backlog management
Proficiency in Microsoft Office for documentation and communication

Why This Role

You won't be handed a spec and told to code. You'll take real ownership of design tasks, with exposure across the full ASIC lifecycle and the opportunity to grow alongside experienced engineers. This is a role where your work matters, your initiative is recognized, and the team values engineers who take ownership and see problems through to resolution.

Salary Note: This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled. Combined Salary Range: USD $142,166.00 - USD $150,000.00 /Yr. Company Overview:

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!

Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans

Apply Now

Refine Your Search

fpga engineer jobs in columbia md

Senior ASIC Digital Design Engineer

Sensor and Detector Design Engineer

Engineer/Developer - Software, Hardware, Research (Capabilities Development Specialist)

Senior ASIC Physical Design Engineer

FPGA Design Engineer Level 2

Lead ASIC Digital Design Engineer

FPGA Verification Engineer Level 3/4 - Linthicum

Digital Design Engineer - Level 5 - Linthicum

FPGA Engineer (part-time)

FPGA Verification Engineer, Bespoke Solutions

FPGA / Reverse Software Engineer

Hardware Engineer (High Performance Computing Digital Design Engineering) - Entry Level (Maryland)

Junior FPGA Design Engineer

Hardware Engineer (High Performance Computing Digital Design Engineering)

FPGA Engineer

Software Engineer (FPGA, Ghidra)-All Levels

Principal FPGA Engineer

Software Engineer 0

2026 Graduate - Mechanical Engineer - Space Science Instrumentation

Software Engineer (Ghidra/FPGA) 2026-0146

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