Top 1692 Design verification engineer Jobs in Cupertino, Ca

ASIC Design Verification Engineer
Cisco Systems —San Jose, CA
- $138,100 - $256,000 a year
- Full-time
- Master's degree
- Bachelor's degree
- Doctor of Philosophy
- Paid parental leave
- Paid holidays
Design Verification Engineer - SoC
Etched —San Jose, CA
- $150,000 - $275,000 a year
- Full-time
- Mid-level
- Office
- Analysis skills
- Health insurance
- Dental insurance
Design Verification Engineer
Cerebras Systems —Sunnyvale, CA
- $190,000 - $230,000 a year
- Full-time
- Computer Science
- Bachelor of Science
- Mid-level
ASIC Design Engineer
Sivaltech —Milpitas, CA
- Mid-level
- Bachelor's degree
Design Engineer
Innogrit —San Jose, CA
- Full-time
- Computer science
- Computer Science
- Master's degree
Quick Apply
Design Verification Engineer - Internal IP
Etched —San Jose, CA
- $150,000 - $275,000 a year
- Full-time
- Mid-level
- Office
- Python
- Health insurance
- Dental insurance
Senior Physical Design Engineer
Capgemini —Santa Clara, CA
- $82,082 - $193,440 a year
- Full-time
- Analysis skills
- In-person
- Senior level
- Paid holidays
- Disability insurance
Senior ASIC Design Verification Engineer
Cisco Systems —San Jose, CA
- $149,100 - $282,000 a year
- Full-time
- Master's degree
- Doctor of Philosophy
- US work authorization
- Paid parental leave
- Paid holidays
Analog Layout Engineer
Capgemini —Santa Clara, CA
- Full-time
- Mentoring
- In-person
- Senior level
- Paid holidays
- Disability insurance
ASIC DFT Engineer
Cisco Systems, Inc. —San Jose, CA
- $125,300 - $186,800 a year
- Full-time
- CAD
- Master's degree
- Senior level
Quick Apply
Senior Hardware Engineer - SoC Electrical Failure Analysis (Hybrid)
Cisco Systems —San Jose, CA
- $146,700 - $277,600 a year
- Full-time
- Hybrid work
- Schematics
- Office
- Master's degree
- Paid parental leave
- Paid holidays
ASIC STA Technical Lead
Cisco Systems —San Jose, CA
- $166,300 - $307,800 a year
- Full-time
- 3 years
- Master's degree
- Analysis skills
- Paid parental leave
- Paid holidays
ASIC Design Verification Engineer, Technical Leader
Cisco Systems —San Jose, CA
- $166,300 - $307,800 a year
- Full-time
- Office
- Master's degree
- 8 years
- Paid parental leave
- Paid holidays
ASIC Design Verification Technical Leader
Cisco Systems —San Jose, CA
- $166,300 - $307,800 a year
- Full-time
- 5 years
- Office
- Master's degree
- Paid parental leave
- Paid holidays
Lead Electrical Design Engineer
Coherent Corp. —Fremont, CA
- Overtime
- 7 years
- Office
- Master's degree
Lead embedded Software Engineer (Board Bring Up)
Capgemini —Santa Clara, CA
- $73,150 - $174,000 a year
- Full-time
- Computer Science
- Software troubleshooting
- System design
- Paid holidays
- Disability insurance
Sr Embedded Software Engineer (Board Bring Up)
Capgemini —Santa Clara, CA
- $73,150 - $174,000 a year
- Full-time
- Computer Science
- 5 years
- Master's degree
- Paid holidays
- Disability insurance
Senior Engineer - Safety & Multimedia / Audio & Camera (iRDK)
Capgemini —Santa Clara, CA
- $68,911 - $161,544 a year
- Full-time
- Computer science
- 7 years
- Computer Science
- Paid holidays
- Disability insurance
Electrical Engineer Signal Integrity and Power Integrity Technical Lead (7400)
Advantest —San Jose, CA
- $129,650 - $200,400 a year
- Full-time
- Background check
- Bachelor of Science
- System design
- Health insurance
- Dental insurance
Quick Apply
Sr System Integration & Test Engineer
ASML —San Jose, CA
- $112,125 - $186,875 a year
- Full-time
- Research
- Master's degree
- Senior level
- Paid holidays
- Health insurance

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ASIC Design Verification Engineer

Cisco Systems -
San Jose, CA

Apply Now

Job Details

Full-time
$138,100 - $256,000 a year

Benefits

Paid parental leave
Paid holidays
Disability insurance
Health insurance
Dental insurance
401(k)
RSU
Parental leave
Vision insurance
401(k) matching
Life insurance

Qualifications

Verilog
Digital circuit design
Scalability

Full Job Description

The application window is expected to close on: 09/10/2026Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

Meet the Team

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Your Impact

As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco’s revolutionary data center solutions. You’ll architect and develop DV infrastructure, create and execute comprehensive test plans, and ensure robust verification and coverage for complex chips. Your collaboration with designers, architects, and software teams will help guarantee seamless integration and optimal performance of Cisco’s hardware platforms. You will:

Architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure.
Build DV environments from scratch for block and cluster levels.
Develop, implement, and enhance test plans and tests for block and cluster verification, using both constraint-random and directed stimulus.
Ensure comprehensive verification coverage through code and functional coverage implementation and review.
Qualify RTL design by running Gate Level Simulations on netlists.
Collaborate with designers, architects, and software teams to debug issues during post-silicon bring-up and integration.
Support design testing in emulation environments.

Minimum Qualifications

Bachelors degree + 5 years of ASIC experience, or Masters degree+ 3 years of ASIC experience, or PhD + 0 years of related experience.
Experience in System Verilog and UVM methodology.
Hands-on experience building reusable and scalable test benches from scratch.
Experience with scripting using Perl and/or Python.

Preferred Qualifications

Experience with forwarding logic, parsers, or P4.
Experience using emulation platforms such as Veloce, Palladium, Zebu, or HAPS.
Knowledge of formal verification tools (e.g., IEV or VC Formal).
Domain knowledge in one or more protocols such as PCIe, CXL, Ethernet, RDMA, DDR, or TCP.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $155,000.00 to $222,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:

10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:

.75% of incentive target for each 1% of revenue attainment up to 50% of quota;
1.5% of incentive target for each 1% of attainment between 50% and 75%;
1% of incentive target for each 1% of attainment between 75% and 100%; and
Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area:
$155,000.00 - $256,000.00

Non-Metro New York state& Washington state:
$138,100.00 - $227,900.00

For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.

** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

Apply Now

Refine Your Search

design verification engineer jobs in cupertino, ca

ASIC Design Verification Engineer

Design Verification Engineer - SoC

Design Verification Engineer

ASIC Design Engineer

Design Engineer

Design Verification Engineer - Internal IP

Senior Physical Design Engineer

Senior ASIC Design Verification Engineer

Analog Layout Engineer

ASIC DFT Engineer

Senior Hardware Engineer - SoC Electrical Failure Analysis (Hybrid)

ASIC STA Technical Lead

ASIC Design Verification Engineer, Technical Leader

ASIC Design Verification Technical Leader

Lead Electrical Design Engineer

Lead embedded Software Engineer (Board Bring Up)

Sr Embedded Software Engineer (Board Bring Up)

Senior Engineer - Safety & Multimedia / Audio & Camera (iRDK)

Electrical Engineer Signal Integrity and Power Integrity Technical Lead (7400)

Sr System Integration & Test Engineer

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