Top 150 Fpga engineer Jobs in Germantown, Md

Senior ASIC Physical Design Engineer
Johns Hopkins Applied Physics Laboratory (APL) —Laurel, MD
- $105,000 - $290,000 a year
- Full-time
- 6 years
- Continuous improvement
- Scripting
- Disability insurance
- Health insurance
Sensor and Detector Design Engineer
Johns Hopkins Applied Physics Laboratory (APL) —Laurel, MD
- $100,000 - $245,000 a year
- Full-time
- Mid-level
- Master's degree
- Analysis skills
- Disability insurance
- Health insurance
Electrical Engineer (Chantilly, VA)
Oxford Global Resources —Chantilly, VA
- $100,000 - $140,000 a year
- Full-time
- Mid-level
- Master's degree
- Travel
- Health insurance
- Dental insurance
Quick Apply
Embedded Software Engineer
Pinnacle Partners, Inc. —Sterling, VA
- $110,000 - $140,000 a year
- Engineering
- Laboratory experience
- Travel
- Relocation assistance
2d
Junior FPGA Design Engineer
Carr Astronautics Corporation —Greenbelt, MD
- Computer science
- Computer Science
- Bachelor of Science
Senior FPGA Development Engineer
Viavi Solutions —Germantown, MD
- $95,900 - $178,100 a year
- Full-time
- 3 years
- Master's degree
- Continuous improvement
- Disability insurance
- Health insurance
7d
Principal FPGA Engineer
Thales —Clarksburg, MD
- $164,452 - $210,133 a year
- Hybrid work
- 6 years
- Bachelor of Science
- System design
- Paid parental leave
- Paid holidays
FPGA Engineer
EndoSec LLC —Reston, VA
- Full-time
- Travel
- Senior level
- Python
Quick Apply
Software Engineer - NTN
Viasat —Germantown, MD
- $140,500 - $261,000 a year
- 12 hour shift
- Computer science
- Computer Science
- Bachelor of Science
FPGA Verification Engineer, Bespoke Solutions
Amazon Development Center U.S., Inc. —Arlington, VA
- $136,000 - $184,000 a year
- Full-time
- Office
- Continuous improvement
- Senior level
- AD&D insurance
- Health insurance
Software Engineer - NTN
Viasat, Inc. —Germantown, MD
- $140,500 - $261,000 a year
- 12 hour shift
- Computer science
- Computer Science
- Bachelor of Science
Digital Signal Processing and FPGA Engineer
Johns Hopkins Applied Physics Laboratory (APL) —Laurel, MD
- $100,000 - $245,000 a year
- Full-time
- Computer Science
- Mid-level
- 3 years
- Disability insurance
- Health insurance
19h
Principal Engineer - FPGA/ASIC Design
Rolls-Royce —Washington, DC
- $152,033 - $247,054 a year
- Full-time
- Hybrid work
- Office
- Windows
- 3 years
- Paid parental leave
- Health savings account
7d
RF Communications Engineer
Johns Hopkins Applied Physics Laboratory (APL) —Laurel, MD
- $85,000 - $195,000 a year
- Full-time
- Computer science
- Computer Science
- Bachelor of Science
- Disability insurance
- Health insurance
Electrical Engineer
Amatriot Group, LLC —Bethesda, MD
- $130,000 - $160,000 a year
- Full-time
- Hybrid work
- Mid-level
- Communication skills
Quick Apply
Hardware in the Loop Engineer
Johns Hopkins Applied Physics Laboratory (APL) —Laurel, MD
- $100,000 - $245,000 a year
- Full-time
- Computer Science
- 5 years
- Bachelor of Science
- Disability insurance
- Health insurance
FPGA/ASIC Design Engineer (Secret) – Reston, VA – 5137
Altimeter Solutions —Reston, VA
- Writing skills
- Master's degree
- Analysis skills
Senior FPGA Engineer
Raytheon —Columbia, MD
- $95,500 - $181,700 a year
- Full-time
- 5 years
- Linux
- In-person
- Paid holidays
- Disability insurance
12h
Electrical Development Engineer
Johns Hopkins Applied Physics Laboratory (APL) —Laurel, MD
- $100,000 - $245,000 a year
- Full-time
- 5 years
- Senior level
- Electrical Engineering
- Disability insurance
- Health insurance
8d
FPGA Engineer
General Atomics —Herndon, VA
- $81,080 - $141,650 a year
- Extended hours
- Engineering
- Laboratory experience
- Business development
- Relocation assistance

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fpga engineer jobs near germantown, md

Senior ASIC Physical Design Engineer

Johns Hopkins Applied Physics Laboratory (APL) -
Laurel, MD

Apply Now

Job Details

Full-time
$105,000 - $290,000 a year

Benefits

Disability insurance
Health insurance
Dental insurance
Flexible spending account
Paid time off
Vision insurance
Life insurance
Retirement plan

Qualifications

Verification (System development task)
Digital circuit design

Full Job Description

Description

Do you love building and prototyping robust electrical systems?

Are you passionate about providing real impact to the country’s toughest national security problems?

If so, we're looking for someone like you to join our team at APL.

The Miniature Device Technologies Group develops highly customized tools and techniques required to carry out missions around the globe. Whether it be a quick reaction need from the field or the long-term development of a novel capability, we work hand in hand with our government sponsors to conceive and realize solutions to their most challenging problems. We leverage our multi-disciplinary set of capabilities in custom application-specific integrated circuits (ASIC), printed circuit board (PCB), embedded software, field-programmable gate array (FPGA), and signal processing design to create ultra-small, low-power solutions that exceed comparable commercial alternatives.

We are seeking an experienced senior physical design ASIC design engineer, to help us advance the state-of-the-art in miniature systems for a wide range of applications. In this role, you will be responsible for all back-end flow aspects, including synthesis, top-level floor-planning, timing analysis and design partitioning to meet timing requirements, SCAN and BIST insertion, and physical verification checks. You will be working closely with the ASIC design team to identify back-end issues, and assist in addressing these issues, both in the RTL and gate-level phases of the design. You will help explore process selection for new proposals and designs, assessing aspects such as achievable size and power, and availability of the necessary design features and intellectual property (IP.) Additionally, you will perform custom physical design as needed, both to complete custom block layouts, and to perform custom modifications necessary at the top level of the ASIC.

As a Senior ASIC Physical Design Engineer...

Your primary responsibility will be digital back-end flow, from synthesis to a completed, verified top-level layout, ready for tapeout submission
You will contribute to process selection for new designs and proposals
You will floorplan the top-level layout of the digital and mixed-signal ASICs
You will perform timing analysis and design partitioning
You will perform SCAN and BIST insertion for maximum defect coverage
You will work with digital designers to debug and address back-end related RTL and gate-level issues
You will perform all physical verification, including DRC, DRC+, MCD, and LVS
You will perform custom physical layout
You may assist with ASIC design environment enhancements and scripting
You will demonstrate initiative by identifying and driving process improvements, and implementing innovative solutions to complex design challenges
You will build and maintain strong working relationships with cross-functional teams, including digital design, verification, and software teams
You will provide leadership and guidance to junior physical design engineers, and contribute to their growth and development
You will collaborate with the team to achieve project goals and objectives, and drive results through effective teamwork and problem-solving
You will foster open communication and collaboration with digital designers, junior physical design engineers, and other stakeholders to ensure seamless project execution

Qualifications

You meet our minimum qualifications for the job if you...

Possess an Associate’s degree in a technical field, or a combination of equivalent level experience/education/certifications.
Are skilled at using Cadence ASIC design tools for back-end flow implementation
Are skilled at using Siemens Calibre physical verification tools
Have 6+ years of experience specifically performing back-end ASIC design
Are able to obtain an Interim Secret level security clearance by your start date and can ultimately obtain a Secret level clearance. If selected, you will be subject to a government security clearance investigation and must meet the requirements for access to classified information. Eligibility requirements include U.S. citizenship.

You'll go above and beyond our minimum requirements if you...

Have experience with custom physical layout in Cadence Virtuoso
Are skilled at using Siemens ASIC design tools for back-end flow implementation
Have extensive knowledge and experience in ASIC technology characterization for process selection
Hold an active clearance and/or have successfully undergone single-scope background investigations in the past.

#LI-AG1

About Us

Why Work at APL?

The Johns Hopkins University Applied Physics Laboratory (APL) brings world-class expertise to our nation’s most critical defense, security, space and science challenges. While we are dedicated to solving complex challenges and pioneering new technologies, what makes us truly outstanding is our culture. We offer a vibrant, welcoming atmosphere where you can bring your authentic self to work, continue to grow, and build strong connections with inspiring teammates.

At APL, we celebrate our differences of perspectives and encourage creativity and bold, new ideas. Our employees enjoy generous benefits, including a robust education assistance program, unparalleled retirement contributions, and a healthy work/life balance. APL’s campus is located in the Baltimore-Washington metro area. Learn more about our career opportunities at https://www.jhuapl.edu/careers.

All qualified applicants will receive consideration for employment without regard to race, creed, color, religion, sex, gender identity or expression, sexual orientation, national origin, age, physical or mental disability, genetic information, veteran status, occupation, marital or familial status, political opinion, personal appearance, or any other characteristic protected by applicable law. APL is committed to providing reasonable accommodation to individuals of all abilities, including those with disabilities. If you require a reasonable accommodation to participate in any part of the hiring process, please contact [email protected].

The referenced pay range is based on JHU APL’s good faith belief at the time of posting. Actual compensation may vary based on factors such as geographic location, work experience, market conditions, education/training and skill level with consideration for internal parity. For salaried employees scheduled to work less than 40 hours per week, annual salary will be prorated based on the number of hours worked. APL may offer bonuses or other forms of compensation per internal policy and/or contractual designation. Additional compensation may be provided in the form of a sign-on bonus, relocation benefits, locality allowance or discretionary payments for exceptional performance. APL provides eligible staff with a comprehensive benefits package including retirement plans, paid time off, medical, dental, vision, life insurance, short-term disability, long-term disability, flexible spending accounts, education assistance, and training and development. Applications are accepted on a rolling basis.

Minimum Rate

$105,000 Annually

Maximum Rate

$290,000 Annually

Apply Now

Refine Your Search

fpga engineer jobs in germantown, md

Senior ASIC Physical Design Engineer

Sensor and Detector Design Engineer

Electrical Engineer (Chantilly, VA)

Embedded Software Engineer

Junior FPGA Design Engineer

Senior FPGA Development Engineer

Principal FPGA Engineer

FPGA Engineer

Software Engineer - NTN

FPGA Verification Engineer, Bespoke Solutions

Software Engineer - NTN

Digital Signal Processing and FPGA Engineer

Principal Engineer - FPGA/ASIC Design

RF Communications Engineer

Electrical Engineer

Hardware in the Loop Engineer

FPGA/ASIC Design Engineer (Secret) – Reston, VA – 5137

Senior FPGA Engineer

Electrical Development Engineer

FPGA Engineer

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