Top 279 Verification engineer Jobs in Gilbert, Az

Advanced ASIC FPGA Verification Engineer for Crypto and Cross Domain Solutions
General Dynamics Mission Systems, Inc —Scottsdale, AZ
- $135,396 - $150,205 a year
- Full-time
- 3 years
- Master's degree
- Analysis skills
Avionics Software Engineer
Belcan —Phoenix, AZ
- $80,000 - $135,000 a year
- Computer Science
- 5 years
- Senior level
- Paid holidays
- Relocation assistance
Quick Apply
6d
Advanced ASIC FPGA Design Engineer for Crypto and Cross Domain Solutions
General Dynamics Mission Systems, Inc —Scottsdale, AZ
- $135,396 - $150,205 a year
- Full-time
- 3 years
- Master's degree
- Analysis skills
Senior Systems Engineer
General Dynamics Mission Systems, Inc —Scottsdale, AZ
- $142,696 - $158,303 a year
- Urgently hiring
- 6 years
- Data analysis skills
- Research
- Paid parental leave
- Health insurance
Sr Principal ASIC FPGA Engineer (Sign-on Bonus Available)
General Dynamics Mission Systems, Inc —Scottsdale, AZ
- $182,139 - $202,060 a year
- Full-time
- Research
- Master's degree
- 8 years
- Paid parental leave
- Health insurance
11d
Module Development Engineer - RF Test
Intel —Phoenix, AZ
- $115,110 - $219,550 a year
- Full-time
- Mid-level
- Master's degree
- Doctor of Philosophy
- Health insurance
Systems Engineering - Integration & Test Engineering- Hardware DevOps Environment
General Dynamics Mission Systems, Inc —Scottsdale, AZ
- $95,384 - $105,817 a year
- Full-time
- Hybrid work
- Mid-level
- Windows
- Master's degree
- Paid parental leave
- Health insurance
Advanced ASIC FPGA Engineer- (Sign-on Bonus Available)
General Dynamics Mission Systems, Inc —Scottsdale, AZ
- $122,785 - $136,215 a year
- Full-time
- Hybrid work
- Data analysis skills
- Research
- 3 years
Information Assurance Engineer
General Dynamics Mission Systems, Inc —Scottsdale, AZ
- $112,924 - $125,275 a year
- Full-time
- Engineering
- 3 years
- Master's degree
- Paid parental leave
- Health insurance
7d
Sr Systems Engineer - 30016_D
BEPC Inc —Phoenix, AZ
- $101 an hour
- Contract
- Background check
- Computer Science
- CAD
- Health insurance
- Dental insurance
Quick Apply
5d
Sr Principal Engineer Electronics
Northrop Grumman —Chandler, AZ
- $122,800 - $184,200 a year
- Overtime
- 3 years
- Master's degree
- Analysis skills
- Paid holidays
- Disability insurance
6d
Sr Systems Engineer
Manpower Engineering —Phoenix, AZ
- $101 an hour
- Computer science
- Computer Science
- CAD
Quick Apply
Field Technical Manager (Queen Creek, AZ)
LG Electronics —Queen Creek, AZ
- $90,000 - $120,000 a year
- Full-time
- 5 years
- English
- Research
- Paid parental leave
- Paid holidays
Quick Apply
Senior Manager, Information Security Operations
Benchmark Electronics, Inc —Tempe, AZ
- Email
- Azure
- Computer Science
- HIPAA
Mixed Signal Verification Engineer
Analog Devices —Chandler, AZ
- Full-time
- Master's degree
- Doctor of Philosophy
- Travel
Technical Staff Engineer - AMS Verification
Microchip Technology —Chandler, AZ
- Full-time
- 11+ years
- Master's degree
- Travel
Senior Test Engineer
Medtronic —Tempe, AZ
- $103,200 - $154,800 a year
- Full-time
- Office
- Master's degree
- Analysis skills
- Health savings account
- Employee stock purchase plan
12d
Sr. Test Engineer
Medtronic —Tempe, AZ
- $103,200 - $154,800 a year
- Full-time
- System design
- Office
- Bachelor's degree
- Health savings account
- Employee stock purchase plan
10d
Physical Verification Engineer
Intel —Phoenix, AZ
- $128,880 - $245,160 a year
- Full-time
- Hybrid work
- Computer Science
- Office
- 3 years
- Health insurance
Technical Staff Engineer - Verification
Microchip Technology —Chandler, AZ
- $91,000 - $232,000 a year
- Full-time
- Bachelor of Science
- 11+ years
- Machine learning
- Employee stock purchase plan
- Health insurance

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verification engineer jobs near gilbert, az

Advanced ASIC FPGA Verification Engineer for Crypto and Cross Domain Solutions

General Dynamics Mission Systems, Inc -
Scottsdale, AZ

Apply Now

Job Details

Full-time
$135,396 - $150,205 a year

Qualifications

Verification (System development task)
Metrics Reporting
Technical report writing
Debugging
Test Planning (Quality assurance practices)

Full Job Description

Basic Qualifications :

Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 5 years of relevant experience; or Master's degree plus a minimum of 3 years of relevant experience.

CLEARANCE REQUIREMENTS: Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.

Responsibilities for this Position:

What You'll Do

Take ownership, lead, develop and maintain UVM-based and non-UVM-based verification environments for complex FPGA designs including cryptographic engines, protocol interfaces, and system-level integration testbenches
Create comprehensive verification plans with functional coverage models, coverage goals, and closure criteria aligned to design specifications
Implement constrained-random stimulus generators, monitors, scoreboards, and functional coverage collectors using SystemVerilog, VHDL and UVM
Drive code coverage (statement, branch, condition, expression, toggle) and functional coverage to closure, analyzing coverage holes and developing targeted stimulus to fill gaps
Develop and maintain automated simulation regression suites that run across multiple test configurations and random seeds
- including nightly regression runs, coverage trend tracking, and automated results reporting using Jenkins, GitLab CI, or similar platforms
Perform assertion-based verification (ABV) using SystemVerilog Assertions (SVA) to capture protocol rules, interface contracts, and design invariants
Debug complex design issues using waveform analysis (QuestaSim, Vivado), assertion failures, and coverage-driven investigation
Collaborate closely with FPGA design engineers during architecture definition to ensure designs are verification-friendly and observable
Review and contribute to design specifications, interface control documents, and verification closure reports
Mentor junior verification engineers on UVM methodology, coverage-driven verification practices, and debugging techniques
Support formal verification activities including property checking, connectivity verification, and equivalence checking where applicable

Required Qualifications

Strong proficiency in SystemVerilog for verification, VHDL for verification including constrained-random stimulus, functional coverage, and assertions
Hands-on experience with UVM (Universal Verification Methodology) including environment architecture, component development, and sequence libraries
Experience with industry-standard simulation tools: QuestaSim/ModelSim Simulators
Demonstrated ability to develop verification plans, define coverage models, and drive coverage to closure
Experience with code coverage metrics (statement, branch, condition, expression, toggle) and coverage analysis workflows
Proficiency in VHDL and/or Verilog for reading and understanding design RTL
Experience with waveform debugging and signal-level analysis
Understanding of AXI-Stream, AXI4, and similar on-chip bus protocols from a verification perspective
Knowledge of clock domain crossing (CDC) verification concepts and metastability analysis
Strong written and verbal communication skills for verification plans, coverage reports, and technical presentations
S. Citizenship and ability to obtain/maintain a Secret security clearance

Preferred Qualifications

Experience verifying cryptographic hardware implementations (AES, GCM, SHA, ECC, RSA, or similar)
- including automated regression management, seed management, and coverage merging
Proficiency in scripting languages (Python, Tcl, Bash, Perl) for verification automation, log parsing, and results analysis
Experience with Xilinx Vivado Design Suite and FPGA-specific verification challenges (timing simulation, post-synthesis/post-route verification)
Knowledge of CDC analysis tools (Questa CDC) and lint/design rule checking tools
Experience with emulation or prototyping platforms for hardware-in-the-loop verification
Knowledge of AXI protocol specification and Questa verification IP (QVIP) usage for protocol compliance checking
Experience with version control (Git), code review processes, and collaborative development workflows

Salary Note: This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled. Combined Salary Range: USD $135,396.00 - USD $150,205.00 /Yr. Company Overview:

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!

Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans

Apply Now

Refine Your Search

verification engineer jobs in gilbert, az

Advanced ASIC FPGA Verification Engineer for Crypto and Cross Domain Solutions

Avionics Software Engineer

Advanced ASIC FPGA Design Engineer for Crypto and Cross Domain Solutions

Senior Systems Engineer

Sr Principal ASIC FPGA Engineer (Sign-on Bonus Available)

Module Development Engineer - RF Test

Systems Engineering - Integration & Test Engineering- Hardware DevOps Environment

Advanced ASIC FPGA Engineer- (Sign-on Bonus Available)

Information Assurance Engineer

Sr Systems Engineer - 30016_D

Sr Principal Engineer Electronics

Sr Systems Engineer

Field Technical Manager (Queen Creek, AZ)

Senior Manager, Information Security Operations

Mixed Signal Verification Engineer

Technical Staff Engineer - AMS Verification

Senior Test Engineer

Sr. Test Engineer

Physical Verification Engineer

Technical Staff Engineer - Verification

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