Top 693 Design verification engineer Jobs in Lakeway, Tx

Senior Staff System IP Design Verification Engineer
Eastridge Workforce Solutions —Austin, TX
- $85 - $93 an hour
- Temporary
- Bachelor of Science
- 11+ years
- Doctor of Philosophy
- 401(k)
- Vision insurance
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CPU Core Design Verification Engineer
Advanced Micro Devices, Inc —Austin, TX
- Hybrid work
- Master's degree
- C++
- Senior level
CPU Design Verification Engineer
Apple —Austin, TX
- Computer science
- Computer Science
- Bachelor of Science
Design Verification Engineer (remote position)
Correct Designs —Austin, TX
- Contract
- Mid-level
- 3 years
- Analysis skills
- Retirement plan
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ASIC Design Verification Engineer
Ericsson —Austin, TX
- 8 hour shift
- Hybrid work
- Master's degree
- Linux
- In-person
- Paid parental leave
- AD&D insurance
Design Verification Engineer
Verilab —Lakeway, TX
- Full-time
- Computer science
- 7 years
- Computer Science
- AD&D insurance
- Paid holidays
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Design Verification Engineer
Correct Designs —Austin, TX
- Contract
- Computer Science
- Mid-level
- 3 years
- Retirement plan
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Digital Design Verification Engineer
OLIX —Austin, TX
- $123,000 a year
- Full-time
- 5 years
- Office
- Residential
- Retirement plan
ASIC Engineer, Design Verification
Meta —Austin, TX
- $114,000 - $172,000 a year
- Computer science
- Computer Science
- Mid-level
ASIC Design Verification Engineer
Advanced Micro Devices, Inc —Austin, TX
- Hybrid work
- Computer Science
- Bachelor of Science
- Engineering
ASIC Design Verification Engineer (Santa Clara, CA)
Qualcomm —Austin, TX
- $126,700 - $190,100 a year
- Engineering
- Mid-level
- 3 years
Design Verification Engineer
Apple —Austin, TX
- $175,000 - $308,500 a year
- Bachelor of Science
- Bachelor's degree
- Senior level
- Employee stock purchase plan
- Health insurance
Design Verification Engineer
Cirrus Logic —Austin, TX
- Full-time
- Hybrid work
- Master's degree
- Doctor of Philosophy
- Senior level
Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU
NVIDIA —Austin, TX
- $136,000 - $264,500 a year
- Full-time
- Computer science
- Computer Science
- 5 years
1d
Design & Verification Engineer, Analog Power Management (7682)
TSMC —Austin, TX
- $120,000 - $170,000 a year
- System design
- Research
- Senior level
Formal Design Verification Engineer
Advanced Micro Devices, Inc —Austin, TX
- Hybrid work
- Mid-level
- Master's degree
- Analysis skills
SoC Physical Design Verification Engineer
Apple —Austin, TX
- $184,700 - $324,800 a year
- Bachelor of Science
- Bachelor's degree
- Senior level
- Employee stock purchase plan
- Health insurance
Design Verification Engineer -Staff
Qualcomm —Austin, TX
- $154,000 - $231,000 a year
- Computer science
- Computer Science
- Mid-level
Senior Design Verification Engineer (remote position)
Correct Designs —Austin, TX
- Contract
- 8 years
- Analysis skills
- In-person
- Retirement plan
Quick Apply
Senior Wire Harness Design Engineer (EWIS)
Saronic Technologies —Austin, TX
- Full-time
- Office
- Mentoring
- Senior level
- Paid parental leave
- Paid holidays
Quick Apply

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Senior Staff System IP Design Verification Engineer

Eastridge Workforce Solutions -
Austin, TX

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Job Details

Temporary | Full-time
$85 - $93 an hour

Benefits

401(k)
Vision insurance

Qualifications

Version control
Verification (System development task)
UNIX
Git
Microcontroller programming
Python

Full Job Description

Created/Revised Date: 07/17/2026

Anticipated Closing Date: 08/15/2026

Job Title: Senior Staff System IP Design Verification Contractor

Location: Austin TX

Salary Pay Range and Other Compensation: $ 85-93.00/hour

Employment Type: Full-Time | Temporary

FLSA Status: Non-Exempt

Schedule: M-F 8-5 p.m.

About the Role:
As a Senior Staff System IP Design Verification Contractor you will contribute to the functional verification of System IP including coherent interconnect and caches. This is a technical individual contributor role with heavily involved hands-on project execution. A strong background in Design Verification and hands-on experience with both block level and top level is required to be successful in this role.

Essential Duties and Responsibilities:

Owning Gate level simulations TB bringup • Owning power aware verification with UPF
Collaborating with Physical design teams, running and debugging gate level simulations
Working with SoC team to debug functional fails during IP bringup and feature execution
Creating test benches, verification environments, stimulus, tests • Collaborating with designers to verify the correctness of a design feature, and resolve fails
Developing assertions, checkers, covergroups, Systemverilog constraints
Debugging and root causing functional fails from regressions
Analyzing code and functional coverage results, performing gap analysis
Helping with Silicon bringup and root causing fails

Qualifications:

Phd/MS/BS in Electrical or Computer Engineering
12+ years industry experience in a design verification role
Expert hands on coding skills in Testbench, Stimulus, checkers development, coverage closure.
Experience with System Verilog, UVM or equivalent
Atleast 5+yrs of experience with Gate level simulations
Knowledge of ARM protocols or equivalent protocols CHI, AXI, ACElite, APB
Experience with Git version control, Unix/Perl/Python scripting
Good written and verbal communication skills

Benefits: Medical, Dental, Vision, 401k, Disabiity and more

Disclaimer: The compensation and benefits information in this posting represent a good faith and reasonable estimate of what it might pay for this position. This information may be modified at any time, subject to applicable law.

Equal Opportunity Employer: Eastridge Workforce Solutions is an Equal Opportunity Employer. We provide an inclusive work environment that celebrates diversity, and all qualified candidates receive consideration for employment without regard to race, color, sex, sexual orientation, gender identity, gender expression, religion, national origin, age (40 and over), disability, military status, genetic information or any other basis protected by applicable federal, state, or local laws. Eastridge Workforce Solutions also prohibits harassment or retaliation of applicants or employees based on any of these protected categories. It is our policy to comply with all applicable federal, state and local laws respecting consideration of unemployment status in making hiring decisions.

Massachusetts Candidates: It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.

Privacy: Information collected and processed as part of your candidate profile, and any job applications, resumes, or other information you choose to submit is subject to Eastridge’s Privacy Policy https://www.eastridge.com/privacy-policy, as well asEastridge’s Pre-Use Notice of Collection and Automated Decision-Making Technologies https://www.eastridge.com/data-collection-notice By applying for this job, you agree to receive calls, AI-generated calls, if applicable, text messages, or emails from Eastridge Workforce Solution, and/or its agents and contracted partners related to confirming assignments and job openings. Message frequency may vary. Standard message and data rates may apply depending on your mobile carrier. To opt out of receiving SMS messages from us at any time, simply reply to the text with “STOP.” Please be aware that message and data rates may apply to any SMS messages sent or received. You can access our SMS Terms and Conditions by visiting https://www.eastridge.com/sms-terms-and-conditions

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design verification engineer jobs in lakeway, tx

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