Top 477 Fpga engineer Jobs in Menlo Park, Ca

Hardware Engineer, FPGA
Normal Computing Corporation —Palo Alto, CA
- $200,000 - $400,000 a year
- Full-time
- Hybrid work
- C++
- Senior level
- Python
Software Engineer, Entry-Level
Muon Space —San Jose, CA
- $142,000 - $169,000 a year
- Full-time
- Hybrid work
- Computer Science
- Office
- Bachelor's degree
- Paid parental leave
- Paid holidays
7d
FPGA Design Engineer
Reliable Robotics Corporation —Mountain View, CA
- $185,000 - $245,000 a year
- Email
- Mid-level
- Electrical Engineering
- 401(k)
FPGA Design Verification Engineer
UST —Mountain View, CA
- $182,000 - $273,000 a year
- Mid-level
- Master's degree
- Fair chance
- Paid jury duty
- Health savings account
Quick Apply
FPGA Engineer, Vehicle Software
Tesla —Palo Alto, CA
- $140,000 - $300,000 a year
- Full-time
- Writing skills
- Mid-level
- Electrical Engineering
- Commuter assistance
- Health savings account
Sensing & Imaging FPGA Engineer
Apple —Cupertino, CA
- $184,700 - $324,800 a year
- Bachelor of Science
- Mid-level
- Analysis skills
- Employee stock purchase plan
- Health insurance
FPGA Engineer
EndoSec LLC —San Jose, CA
- Full-time
- Travel
- Senior level
- Python
Quick Apply
ASIC Design Engineer - IP Integration & Implementation
Apple —Sunnyvale, CA
- $184,700 - $324,800 a year
- Writing skills
- Bachelor's degree
- Senior level
- Employee stock purchase plan
- Health insurance
12d
Mechatronics Engineer
Innate —Palo Alto, CA
- Full-time
- Mid-level
Senior FPGA Design Verification Engineer
Intuitive Surgical —Sunnyvale, CA
- $152,000 - $257,200 a year
- Day shift
- Machine learning
- Fair chance
- In-person
Sr. FPGA Design Engineer
Reliable Robotics Corporation —Mountain View, CA
- $215,000 - $300,000 a year
- Email
- Senior level
- Electrical Engineering
Sr. FPGA Engineer, Certification
Reliable Robotics Corporation —Mountain View, CA
- $215,000 - $300,000 a year
- Email
- Experience equivalent to degree accepted
- Senior level
- Electrical Engineering
Senior FPGA Prototyping Platform Engineer
NVIDIA —Santa Clara, CA
- $168,000 - $310,500 a year
- Full-time
- Management
- 5 years
- Bachelor of Science
FPGA Engineer (eInfochips Inc)
Arrow Electronics, Inc. —Mountain View, CA
- Full-time
- Travel
- In-person
- Senior level
- Health savings account
- Paid holidays
5d
FPGA Design Engineer
Teradyne —San Jose, CA
- $135,400 - $216,600 a year
- Windows
- 3 years
- Master's degree
- Paid holidays
- Disability insurance
FPGA / VLSI Engineer
E-Space —Saratoga, CA
- $120,000 - $220,000 a year
- Weekends as needed
- Office
- Master's degree
- Analysis skills
- Paid holidays
- Paid time off
Electrical Design Engineer
Siemens Healthineers —Palo Alto, CA
- $129,900 - $178,618 a year
- Full-time
- Hybrid work
- 7 years
- Bachelor of Science
- Laboratory experience
- Disability insurance
- Health insurance
Quick Apply
5d
Verification Engineer
Delos Data Inc —Palo Alto, CA
- $160,000 - $220,000 a year
- Full-time
- Remote
- 7 years
- Master's degree
- Analysis skills
- 401(k)
Quick Apply
GPU Verification Engineer - New College Grad 2026
NVIDIA —Santa Clara, CA
- $100,000 - $189,750 a year
- Full-time
- Computer science
- Computer Science
- Master's degree
2h
Senior FPGA Design Engineer
Teradyne —San Jose, CA
- $170,400 - $272,600 a year
- Bachelor of Science
- Windows
- 8 years
- Paid holidays
- Disability insurance

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Hardware Engineer, FPGA

Normal Computing Corporation
Palo Alto, CA

Apply Now

Job Details

Full-time
$200,000 - $400,000 a year

Qualifications

AI models
Regression testing implementation
Inter-Integrated Circuit (I2C) protocol
Software engineering
Engineering development testing
Electronics functional testing
Tooling
FPGA
Procurement
Defect analysis
VHDL
Universal asynchronous receiver-transmitter (UART) protocol
Verilog
C++
Docker
Model deployment
Computer hardware
System validation
Serial peripheral interface (SPI) protocol
Oscilloscopes
FPGA circuit design
Root cause analysis
Logic analyzers
Implementing machine learning algorithms
DevOps automation
Senior level
Vivado
Prototypes
GitLab
Python

Full Job Description

About Normal Computing

Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. Conventional chips spend most of their energy forcing determinism onto physics; ours compute with it. Stochastic, in-memory, asynchronous: the result is 10-100× more AI inference per dollar, per watt.

We co-design the full stack: AI-native EDA systems in production with the world's largest semiconductor companies, and the advanced ASICs they make possible. Backed by $85M+ from the world's leading deep-tech investors and built by scientists, engineers, and operators from the labs that built modern computing.

Normal works as one team across New York, Silicon Valley, London, Copenhagen, and Seoul. We hire people who want the hardest version of their craft, across every discipline, at every seniority.

The Role

Validating conventional silicon is a solved discipline. Validating silicon that computes with noise is not, and you will be the one who figures out how. As our FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early software development, and building the test infrastructure for post-silicon bring-up and characterization. Your scope spans the entire FPGA lifecycle: selecting hardware platforms, implementing complex RTL, debugging in the lab, and writing the software that drives it all, working daily with our silicon, EDA, and research teams.

What You Will Own

FPGA Platform Ownership: Lead the selection, procurement, and bring-up of FPGA prototyping platforms (e.g., HAPS, VCU118/VPK180-class boards, or custom hardware) for pre-silicon RTL validation and software development.
RTL Implementation: Adapt and implement complex ASIC RTL onto FPGA targets, including multi-clock-domain architectures, CDC bridges, and timing closure on dense designs.
IP Integration: Integrate in-house designs with third-party and vendor IP; serve as the expert on the AMD/Xilinx ecosystem (Vivado IP Integrator, transceivers, memory controllers).
High-Speed Interfaces: Design, implement, and validate high-speed I/O with a focus on PCIe: our accelerators ship as PCIe cards in standard servers.
Post-Silicon Validation: Build FPGA-based "tester" designs for silicon bring-up, device characterization, and automated test environments.
Hardware-Software Stack: Develop the software layer around the hardware: Python/C++ hardware abstraction, register-map generation, and automated build and regression flows.
Lab Debug: Root-cause complex timing and functional issues in real time using ILA/Vivado Analyzer, oscilloscopes, logic analyzers, and BER/eye-diagram characterization of high-speed links.

What Makes You a Great Fit

Proven industry experience taking FPGA designs from RTL through timing closure to validated hardware, ideally in an ASIC prototyping, emulation, or high-growth hardware environment.
Expert-level SystemVerilog and/or VHDL for synthesis, with deep proficiency in Xilinx Vivado (synthesis, place & route, timing closure, IP catalog).
Hands-on experience implementing and debugging PCIe, plus AXI/AHB, SPI, UART, JTAG, and other common interfaces.
Strong Python for automation, test, and build tooling.
Strong board-level bring-up and lab debugging skills on real hardware.
Startup mindset: you work independently, pivot quickly, and run at ambiguous problems that span hardware, software, and physics.

Bonus Points

Verification frameworks like Cocotb or UVM
Experience deploying ML models to FPGAs (hls4ml, FINN, or custom NN-to-RTL flows), or building real-time, sub-microsecond signal processing pipelines.
Mixed-signal ASIC exposure: digital front-ends, ADC/DAC interfaces, or analog compute.
SERDES tuning and signal integrity fundamentals.
CI/CD for hardware (GitLab CI, Docker-based build and test).

Equal Employment Opportunity Statement

Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.

Accessibility Accommodations

Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at [email protected].

Privacy Notice

By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.

Compensation Range: $200K - $400K

Apply Now

Refine Your Search

fpga engineer jobs in menlo park, ca

Hardware Engineer, FPGA

Software Engineer, Entry-Level

FPGA Design Engineer

FPGA Design Verification Engineer

FPGA Engineer, Vehicle Software

Sensing & Imaging FPGA Engineer

FPGA Engineer

ASIC Design Engineer - IP Integration & Implementation

Mechatronics Engineer

Senior FPGA Design Verification Engineer

Sr. FPGA Design Engineer

Sr. FPGA Engineer, Certification

Senior FPGA Prototyping Platform Engineer

FPGA Engineer (eInfochips Inc)

FPGA Design Engineer

FPGA / VLSI Engineer

Electrical Design Engineer

Verification Engineer

GPU Verification Engineer - New College Grad 2026

Senior FPGA Design Engineer

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