Top 1779 Verification engineer Jobs in Milpitas, Ca

ASIC Design Verification Technical Leader
Cisco Systems —San Jose, CA
- $166,300 - $307,800 a year
- Full-time
- 5 years
- Office
- Master's degree
- Paid parental leave
- Paid holidays
ASIC STA Technical Lead
Cisco Systems —San Jose, CA
- $166,300 - $307,800 a year
- Full-time
- 3 years
- Master's degree
- Analysis skills
- Paid parental leave
- Paid holidays
Design Verification Engineer (Einfochips)
Arrow Electronics, Inc. —San Jose, CA
- Full-time
- 6 years
- Office
- Travel
- Health savings account
- Disability insurance
Senior Physical Design Engineer
Capgemini —Santa Clara, CA
- $82,082 - $193,440 a year
- Full-time
- Analysis skills
- In-person
- Senior level
- Paid holidays
- Disability insurance
ASIC Design Verification Engineer
Cisco Systems —San Jose, CA
- $138,100 - $256,000 a year
- Full-time
- Master's degree
- Bachelor's degree
- Doctor of Philosophy
- Paid parental leave
- Paid holidays
Senior Hardware Engineer - SoC Electrical Failure Analysis (Hybrid)
Cisco Systems —San Jose, CA
- $146,700 - $277,600 a year
- Full-time
- Hybrid work
- Schematics
- Office
- Master's degree
- Paid parental leave
- Paid holidays
Senior ASIC Design Verification Engineer
Cisco Systems —San Jose, CA
- $149,100 - $282,000 a year
- Full-time
- Master's degree
- Doctor of Philosophy
- US work authorization
- Paid parental leave
- Paid holidays
Lead embedded Software Engineer (Board Bring Up)
Capgemini —Santa Clara, CA
- $73,150 - $174,000 a year
- Full-time
- Computer Science
- Software troubleshooting
- System design
- Paid holidays
- Disability insurance
ASIC DFT Engineer
Cisco Systems, Inc. —San Jose, CA
- $125,300 - $186,800 a year
- Full-time
- CAD
- Master's degree
- Senior level
Quick Apply
Test Supervisor
dB Control —Fremont, CA
- $80,000 - $100,000 a year
- Full-time
- Mid-level
- Analysis skills
- Bachelor's degree
- Health savings account
- Health insurance
Quick Apply
Senior Engineer - Safety & Multimedia / Audio & Camera (iRDK)
Capgemini —Santa Clara, CA
- $68,911 - $161,544 a year
- Full-time
- Computer science
- 7 years
- Computer Science
- Paid holidays
- Disability insurance
ASIC Design Verification Engineer, Technical Leader
Cisco Systems —San Jose, CA
- $166,300 - $307,800 a year
- Full-time
- Office
- Master's degree
- 8 years
- Paid parental leave
- Paid holidays
ASIC Engineering Technical Leader (onsite) - 2014979
Cisco Systems —San Jose, CA
- $151,300 - $281,800 a year
- Full-time
- Hybrid work
- Computer Science
- System design
- Research
- Paid parental leave
- Paid holidays
Sr. Electron Optics Engineer
ASML —San Jose, CA
- Full-time
- Research
- Master's degree
- Senior level
- Paid holidays
- Health insurance
Lead Electrical Design Engineer
Coherent Corp. —Fremont, CA
- Overtime
- 7 years
- Office
- Master's degree
Sr Embedded Software Engineer (Board Bring Up)
Capgemini —Santa Clara, CA
- $73,150 - $174,000 a year
- Full-time
- Computer Science
- 5 years
- Master's degree
- Paid holidays
- Disability insurance
Senior Hardware Post-Silicon Validation Engineer (Hybrid)
Cisco Systems —San Jose, CA
- $149,100 - $282,000 a year
- Full-time
- Hybrid work
- Master's degree
- Doctor of Philosophy
- US work authorization
- Paid parental leave
- Paid holidays
Senior Electrical Firmware Engineer
TMP Worldwide India Private Limited for ERS US —Sunnyvale, CA
- $78,000 - $148,000 a year
- Email
- In-person
- Senior level
- AD&D insurance
- Paid holidays
Quick Apply
Sr System Integration & Test Engineer
ASML —San Jose, CA
- $112,125 - $186,875 a year
- Full-time
- Research
- Master's degree
- Senior level
- Paid holidays
- Health insurance
Senior ASIC RTL Design Engineer
Proficient Design LLC —Sunnyvale, CA
- $150,000 - $200,000 a year
- Contract
- Master's degree
- In-person
- Senior level
Quick Apply
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ASIC Design Verification Technical Leader

Cisco Systems -
San Jose, CA

Apply Now

Job Details

Full-time
$166,300 - $307,800 a year

Benefits

Paid parental leave
Paid holidays
Disability insurance
Health insurance
Dental insurance
401(k)
RSU
Parental leave
Vision insurance
401(k) matching
Life insurance

Qualifications

SystemVerilog

Full Job Description

The application window is expected to close on: 10/19/2026Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

This role requires being onsite in San Jose, CA at least 4 days/week.

Meet the Team

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Your Impact

Lead the planning and execution of ASIC verification for complex networking SoCs, ensuring high-quality and predictable project execution.
Drive verification strategy, testplan development, coverage closure, and execution across multiple IPs and subsystem-level verification efforts.
Provide technical leadership and mentorship to verification engineers, promoting best practices and technical excellence.
Develop and enhance scalable, reusable verification environments, infrastructure, and methodologies using SystemVerilog/UVM.
Collaborate closely with architecture, RTL, emulation, FPGA, and post-silicon teams to enable efficient debug and successful silicon bring-up.
Lead complex debug efforts, perform root cause analysis, and drive issues to closure across simulation, emulation, and silicon.
Champion continuous improvements in verification productivity, automation, regression efficiency, and quality metrics.
Evaluate and adopt new verification technologies, methodologies, and industry best practices to improve verification effectiveness.

Minimum Qualifications

Bachelor's degree with 10+ years of related experience, or Master's degree with 7+ years of related experience, or Ph.D. with 5+ years of related experience.
Strong experience with SystemVerilog, UVM, and modern verification methodologies, including hardware emulation.
Experience developing and executing verification strategies for complex ASIC or SoC programs.
Experience leading verification teams or serving as the technical lead for complex verification projects.
Proficiency in scripting languages such as Python or Perl

Preferred Qualifications

Experience with Datacenter, Hyperscaler, AI, or networking ASICs.
Deep understanding of high-speed protocols (e.g., PCIe, Ethernet, CXL, HBM, DDR) and large-scale SoC architectures.
Hands-on experience with hardware emulation platforms such as FPGA prototyping, Cadence Palladium, Siemens Veloce/StratoCS, or Synopsys ZeBu.
Experience with silicon bring-up, post-silicon validation, and debug.
Experience optimizing verification productivity, regression infrastructure, and automation.
Strong technical leadership, communication, collaboration, and mentoring skills

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $186,900.00 to $267,700.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:

10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:

.75% of incentive target for each 1% of revenue attainment up to 50% of quota;
1.5% of incentive target for each 1% of attainment between 50% and 75%;
1% of incentive target for each 1% of attainment between 75% and 100%; and
Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area:
$186,900.00 - $307,800.00

Non-Metro New York state& Washington state:
$166,300.00 - $274,100.00

For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.

** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

Apply Now

Refine Your Search

verification engineer jobs in milpitas, ca

ASIC Design Verification Technical Leader

ASIC STA Technical Lead

Design Verification Engineer (Einfochips)

Senior Physical Design Engineer

ASIC Design Verification Engineer

Senior Hardware Engineer - SoC Electrical Failure Analysis (Hybrid)

Senior ASIC Design Verification Engineer

Lead embedded Software Engineer (Board Bring Up)

ASIC DFT Engineer

Test Supervisor

Senior Engineer - Safety & Multimedia / Audio & Camera (iRDK)

ASIC Design Verification Engineer, Technical Leader

ASIC Engineering Technical Leader (onsite) - 2014979

Sr. Electron Optics Engineer

Lead Electrical Design Engineer

Sr Embedded Software Engineer (Board Bring Up)

Senior Hardware Post-Silicon Validation Engineer (Hybrid)

Senior Electrical Firmware Engineer

Sr System Integration & Test Engineer

Senior ASIC RTL Design Engineer

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