Top 50 Design engineer Jobs in New Mexico

Early Career R&D Electronics Engineer - Digital IC Design, Onsite
Sandia National Laboratories —Albuquerque, NM
- $102,400 - $199,700 a year
- Full-time
- Pass drug screening
- Bachelor's degree
- In-person
- Relocation assistance
- Health insurance
OSP Design Engineer
CCI Systems, Inc. —Farmington, NM
- Full-time
- Clean driving record
- Research
- Mid-level
- Paid training
- On-the-job training
Quick Apply
Senior/Principal Radio Frequency (RF) Engineer - Global Security Design, Development, and Qualification, Onsite
Sandia National Laboratories —Albuquerque, NM
- $117,500 - $235,700 a year
- Full-time
- Management
- 5 years
- Pass drug screening
- Relocation assistance
- Health insurance
8d
Structural Design Engineer (Civil/Truss)
Alpine —New Mexico
- $70,000 - $100,000 a year
- Full-time
- Hybrid work
- Mid-level
- Office
- Analysis skills
- Paid holidays
- Parental leave
Senior Design Engineer 1
Albuquerque, NM
- Microsoft Word
- Schematics
- Basic math
- Health savings account
- Paid holidays
Bridge Design Project Engineer III
AECOM —Albuquerque, NM
- $85,000 - $135,000 a year
- Full-time
- Hybrid work
- Bachelor of Science
- Office
- Bachelor's degree
- AD&D insurance
- Employee stock purchase plan
Design Engineering Scientist (Scientist 2)
Los Alamos National Laboratory —Los Alamos, NM
- $106,400 - $176,000 a year
- Email
- 18 years or older
- Pass drug screening
- Mid-level
- Paid parental leave
- Disability insurance
Water/Wastewater Design Engineer
MacKay —Albuquerque, NM
- $105,000 - $130,000 a year
- Remote
- Background check
- 5 years
- Bachelor of Science
- Health savings account
- Paid holidays
South Region Design Senior Engineer (DOT/GO/PINF #19082)
State of New Mexico —Las Cruces, NM
- $40.28 - $64.45 an hour
- Extended hours
- Bachelor of Science
- Office
- 3 years
3d
Senior Design Engineer 4
Edgewater Technical Associates —Los Alamos, NM
- Weekends as needed
- Management
- Engineering
- Analysis skills
- Disability insurance
- Health insurance
Quick Apply
Airport Design Engineer
Lochner —Albuquerque, NM
- Full-time
- Civil engineering
- Bachelor of Science
- Pass drug screening
- Wellness program
- Paid parental leave
Senior Design Engineer #3136 (3745)
Navarro Inc. —Los Alamos, NM
- Full-time
- Engineering
- Construction experience
- Senior level
- AD&D insurance
- Paid holidays
Quick Apply
Senior FPGA / Digital Design Engineer
AeroVironment —Albuquerque, NM
- Bachelor of Science
- Mentoring
- Senior level
- Paid holidays
- Health insurance
RF PCBA Design and Test Engineer
AeroVironment —Albuquerque, NM
- $111,500 - $170,000 a year
- Full-time
- Office
- Master's degree
- SQL
- Paid holidays
- Health insurance
Senior Design Engineer - Water/Wastewater Treatment
MacKay —Albuquerque, NM
- $130,000 - $155,000 a year
- Remote
- Background check
- Bachelor of Science
- Pass drug screening
- Health savings account
- Paid holidays
Senior Design Engineer
GEM Technologies, Inc. —Los Alamos, NM
- Full-time
- Engineering
- Analysis skills
- Team management
- Health savings account
- Paid holidays
Quick Apply
Senior/Principal Electrical Engineer - Space Systems Design, Onsite
Sandia National Laboratories —Albuquerque, NM
- $117,500 - $235,700 a year
- Full-time
- 5 years
- Pass drug screening
- Bachelor's degree
- Relocation assistance
- Health insurance
3d
Senior Engineer - Bridge Design (DOT/GO/PINF #10101505)
State of New Mexico —Santa Fe, NM
- $40.28 - $64.45 an hour
- Extended hours
- Bachelor of Science
- Office
- 3 years
Web Programmer & UX Designer
New Mexico Junior College —Hobbs, NM
- $64,313 - $69,614 a year
- Full-time
- Computer Science
- Mid-level
- University
Quick Apply
Senior Photonic Integrated Circuit (PIC) Design - 745
Quantinuum —Albuquerque, NM
- $148,000 - $185,000 a year
- Full-time
- Pass drug screening
- Master's degree
- Mentoring
- Paid parental leave
- Paid holidays
6d

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Early Career R&D Electronics Engineer - Digital IC Design, Onsite

Sandia National Laboratories -
Albuquerque, NM

Apply Now

Job Details

Full-time
$102,400 - $199,700 a year

Benefits

Relocation assistance
Health insurance
401(k)

Qualifications

Engineering research
Technical research projects
Research & development

Full Job Description

About Sandia

Sandia National Laboratories is the nation’s premier science and engineering lab for national security and technology innovation, with teams of specialists focused on cutting-edge work in a broad array of areas. Some of the main reasons we love our jobs:

Challenging work with amazing impact that contributes to security, peace, and freedom worldwide
Extraordinary co-workers
Some of the best tools, equipment, and research facilities in the world
Career advancement and enrichment opportunities
Flexible work arrangements for many positions include 9/80 (work 80 hours every two weeks, with every other Friday off) and 4/10 (work 4 ten-hour days each week) compressed workweeks, part-time work, and telecommuting (a mix of onsite work and working from home)
Generous vacation, strong medical and other benefits, competitive 401k, learning opportunities, relocation assistance and amenities aimed at creating a solid work/life balance*

World-changing technologies. Life-changing careers. Learn more about Sandia at: http://www.sandia.gov

These benefits vary by job classification.

What Your Job Will Be Like

We are seeking a highly motivated Digital IC Design Engineer to join a collaborative team delivering advanced ASIC solutions for mission and laboratory customers. This role focuses on translating system needs into robust, verifiable RTL through tapeout, with close coordination across analog/MEMS/photonics and physical-design partners.

On any given day, you may be called on to:

Review project schedules and milestones (tapeout targets, design reviews, lab deliverables) with the PI/tech lead, identify blockers (PDK/tool updates, interface questions, verification gaps), and drive closure
Convert customer/mission needs into clear block-level specifications (performance, power, area, radiation tolerance, interfaces, testability) and maintain requirements-to-design traceability
Develop and maintain RTL (control, datapath/DSP, interfaces), integrate IP, and implement clean CDC/reset strategies and appropriate low-power/clocking techniques.
Build and extend verification environments; run regressions; analyze failures; close coverage; and perform lint, CDC, and formal checks with documented evidence for reviews
Run or coordinate synthesis and implementation handoff; review timing/power reports; debug critical paths; and iterate with physical design to meet constraints
Collaborate closely with analog/MEMS/photonics teams on mixed-signal interfaces (ADC/DAC timing, bias/control, sensor protocols) and validate behavior against system-level models
Apply knowledge of advanced integration constraints (I/O, routing, packaging, thermal, signal integrity; 2.5D/3D integration) to architecture and implementation tradeoffs
Incorporate resiliency features as required (TMR/EDAC, scrubbing, watchdogs, redundancy) and support radiation/reliability analysis and trade studies
Define scan/BIST strategy, test hooks and observability for lab bring-up, and support post-silicon debug planning and test-vector development
Maintain design documentation (ICDs, review packages) and present at peer reviews; capture decisions and action items for configuration control
Contribute to R&D efforts in advanced signal/data processing (e.g., focal-plane arrays, radiation detector readouts, neuromorphic concepts, quantum support circuits) through simulation and small test chips
Follow configuration management, data handling, and tool/PDK usage practices, coordinating with foundry/MPW schedules and internal processes as applicable

Due to the nature of the work, the selected applicant must be able to work onsite.

Salary Range

$102,400 - $199,700

Salary range is estimated, and actual salary will be determined after consideration of the selected candidate's experience and qualifications, and application of any approved geographic salary differential.

Qualifications We Require

A Bachelor's degree in a relevant discipline, or an equivalent combination of directly relevant education and engineering or scientific experience that demonstrates the knowledge, skills, and ability to perform independent research and development
Ability to obtain and maintain a DOE Q clearance

Qualifications We Desire

Strong proficiency in RTL design using Verilog/SystemVerilog, including synthesizable coding practices
Experience with digital design fundamentals such as pipelining, clock-domain crossing, FSMs, datapath/control partitioning, and timing closure
Ability to use EDA toolflows for synthesis, static timing analysis (STA), linting, CDC/RDC checks, and formal verification
Solid understanding of CMOS device physics, digital logic, noise margins, and process technology scaling effects
Hands-on experience with simulation and verification using UVM or similar methodologies
Familiarity with SoC integration, bus protocols (AXI/AHB/APB), and IP block-level design.
Competency in power aware design, low power techniques (clock gating, power gating), and PPA tradeoff analysis
Competency in Radiation hardened design
Ability to read and interpret schematics, timing diagrams, and physical design constraints (SDC)
Ability to collaborate with analog, physical design, firmware, and systems teams to ensure successful chip integration and tape out

About Our Team

The Mixed-Signal ASIC/SoC Products Department specializes in developing analog and digital integrated circuits (IC) for a variety of applications that require high reliability, high performance or specialized integrated circuits. The department develops a wide range of Application Specific Integrated Circuits (ASICs) for a variety of government applications. Circuit designs include read-out electronics, data acquisition, information processing, encryption/decryption, radiation-hardened electronics, trusted computing, and control circuit applications. Customers include DOE weapons systems, satellite systems, the intelligence community, Army, Air Force, and commercial industry. Mission success is assured by employing disciplined design methodologies and state-of-the-art computer aided engineering (CAE) tools.

Posting Duration

This posting will be open for application submissions for a minimum of three (3) calendar days, including the 'posting date'. Sandia reserves the right to extend the posting date at any time.

Security Clearance

Sandia is required by DOE to conduct a pre-employment drug test and background review that includes checks of personal references, credit, law enforcement records, and employment/education verifications. Applicants for employment need to be able to obtain and maintain a DOE Q-level security clearance, which requires U.S. citizenship. If you hold more than one citizenship (i.e., of the U.S. and another country), your ability to obtain a security clearance may be impacted.

Applicants offered employment with Sandia are subject to a federal background investigation to meet the requirements for access to classified information or matter if the duties of the position require a DOE security clearance. Substance abuse or illegal drug use, falsification of information, criminal activity, serious misconduct or other indicators of untrustworthiness can cause a clearance to be denied or terminated by DOE, resulting in the inability to perform the duties assigned and subsequent termination of employment.

EEO

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, or veteran status and any other protected class under state or federal law.

NNSA Requirements for MedPEDs

If you have a Medical Portable Electronic Device (MedPED), such as a pacemaker, defibrillator, drug-releasing pump, hearing aids, or diagnostic equipment and other equipment for measuring, monitoring, and recording body functions such as heartbeat and brain waves, if employed by Sandia National Laboratories you may be required to comply with NNSA security requirements for MedPEDs.

If you have a MedPED and you are selected for an on-site interview at Sandia National Laboratories, there may be additional steps necessary to ensure compliance with NNSA security requirements prior to the interview date.

Apply Now

Refine Your Search

design engineer jobs in new mexico

Early Career R&D Electronics Engineer - Digital IC Design, Onsite

OSP Design Engineer

Senior/Principal Radio Frequency (RF) Engineer - Global Security Design, Development, and Qualification, Onsite

Structural Design Engineer (Civil/Truss)

Senior Design Engineer 1

Bridge Design Project Engineer III

Design Engineering Scientist (Scientist 2)

Water/Wastewater Design Engineer

South Region Design Senior Engineer (DOT/GO/PINF #19082)

Senior Design Engineer 4

Airport Design Engineer

Senior Design Engineer #3136 (3745)

Senior FPGA / Digital Design Engineer

RF PCBA Design and Test Engineer

Senior Design Engineer - Water/Wastewater Treatment

Senior Design Engineer

Senior/Principal Electrical Engineer - Space Systems Design, Onsite

Senior Engineer - Bridge Design (DOT/GO/PINF #10101505)

Web Programmer & UX Designer

Senior Photonic Integrated Circuit (PIC) Design - 745

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