Top 67 Integration lead Jobs in Santa Cruz Ca

Lead ASIC DFT Engineer
Cyient —San Jose, CA
- $80 - $85 an hour
- Full-time
- Analysis skills
- Mentoring
- In-person
Quick Apply
Operations Lead
Swellcycle Inc. —Santa Cruz, CA
- From $80,000 a year
- Weekends as needed
- 5 years
- Mid-level
- Team management
- Health insurance
- 401(k)
Quick Apply
Lead Electrical Systems Engineer
Leidos —California
- $131,300 - $237,350 a year
- Full-time
- Hybrid work
- Engineering
- Master's degree
- Team management
3d
Lead Electrical Systems Engineer
Leidos —California
- $131,300 - $237,350 a year
- Full-time
- Hybrid work
- Engineering
- Master's degree
- Team management
3d
Lead Electrical Systems Engineer
Leidos —California
- $131,300 - $237,350 a year
- Full-time
- Hybrid work
- Engineering
- Master's degree
- Team management
3d
Lead Integration Architect
Agilent Technologies Inc —Santa Clara, CA
- $153,040 - $286,950 a year
- Full-time
- System design
- Laboratory experience
- Senior level
5d
People Operations Lead
Heron Power —Scotts Valley, CA
- $125,000 - $170,000 a year
- Full-time
- 5 years
- Mid-level
- Bachelor's degree
Instructional Technology Lead
University of California Santa Cruz —Santa Cruz, CA
- $71,600 - $98,000 a year
- Weekends as needed
- High school
- Mid-level
- Master's degree
AI Applications & Data Analytics Lead
Granite Construction Inc. —Watsonville, CA
- $95,753 - $175,018 a year
- Computer science
- Computer Science
- Ability to walk for extended periods
- Health savings account
- Paid holidays
Quick Apply
5d
System Test Software Lead
Joby Aviation —Santa Cruz, CA
- $158,500 - $257,200 a year
- Full-time
- Computer science
- Computer Science
- Bachelor of Science
- Employee stock purchase plan
- Disability insurance
Camera Image Sensor Digital Design Engineer Lead
Apple —Cupertino, CA
- $175,500 - $311,700 a year
- Bachelor's degree
- Senior level
- 10 years
- Employee stock purchase plan
- Health insurance
Environmental Health and Safety (EHS) Lead
Joby Aviation —Santa Cruz, CA
- $129,700 - $232,300 a year
- Full-time
- Bachelor of Science
- 3 years
- Bachelor's degree
- Employee stock purchase plan
- Disability insurance
11d
Lead Compliance Engineer
Heron Power —Scotts Valley, CA
- $150,000 - $198,000 a year
- Full-time
- 7 years
- Research
- Master's degree
Verification & Validation Lead
Capstan Medical, Inc. —Santa Cruz, CA
- Hybrid work
- Computer Science
- 5 years
- Bachelor of Science
Quick Apply
Senior Technical Product Manager - Data Governance Technology Platform Lead
U.S. Bank National Association —Cupertino, CA
- $148,495 - $174,700 a year
- Full-time
- Office
- 8 years
- Product management
- Paid holidays
- Disability insurance
Core Software Services Lead
Joby Aviation —Santa Cruz, CA
- $183,000 - $252,000 a year
- Full-time
- System design
- C++
- Mentoring
- Employee stock purchase plan
- Disability insurance
ASIC Chip Design Lead
Eridu AI —Saratoga, CA
- $250,000 - $280,000 a year
- Full-time
- Analysis skills
- Senior level
Data Platform Security & Governance Leader
U.S. Bank National Association —Cupertino, CA
- $148,495 - $174,700 a year
- Full-time
- Office
- 8 years
- Product management
- Paid holidays
- Disability insurance
Software Integration Lead – 5G CORE
E-Space —Saratoga, CA
- $180,000 - $220,000 a year
- Weekends as needed
- Computer Science
- System design
- 11+ years
- Paid holidays
- Paid time off
Lead Embedded SW Engineer, Hardware Emulation
Joby Aviation —Santa Cruz, CA
- $139,500 - $224,400 a year
- Full-time
- Computer Science
- Schematics
- Bachelor of Science
- Employee stock purchase plan
- Disability insurance

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Lead ASIC DFT Engineer

Cyient -
San Jose, CA

Quick Apply

Job Details

Full-time | Contract
$80 - $85 an hour

Qualifications

Analog circuit design
Engineering development testing
Electronics functional testing
Integrated circuits (ICs)
Ramps
Analysis skills
SoC
System architecture design
Simulation tools
Root cause analysis
Test analysis
Python
Debugging
Cross-functional communication

Full Job Description

Title - Lead ASIC DFT Engineer

Location – San Jose, CA.

Duration - Contract

Job Description

Experience

10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Key Responsibilities

Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
Act as a technical escalation point for advanced DFT and post-silicon debug issues.
Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

Required Skills & Qualifications

Strong hands-on experience in ASIC DFT with end-to-end ownership.
Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
Experience with MBIST implementation and verification; SMS experience preferred.
Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
Proven post-silicon debug and silicon bring-up experience.
Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
Strong communication skills and the ability to work independently with minimal ramp-up.

Preferred Experience

MBIST post-silicon validation.
ATPG simulations and fault coverage debug.
DFT RTL, DFD, DFT verification, and IP-level DFT integration.
DFT SDC creation and DFT timing closure support.
Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
TCL/PERL scripting for DFT automation, reporting, and debug.
Experience working across multiple ASIC technology nodes and complex product development cycles.
Familiarity with yield learning, diagnosis, and manufacturing test optimization.

Pay: $80.00 - $85.00 per hour

Work Location: In person

Quick Apply

Refine Your Search

integration lead jobs in santa cruz ca

Lead ASIC DFT Engineer

Operations Lead

Lead Electrical Systems Engineer

Lead Electrical Systems Engineer

Lead Electrical Systems Engineer

Lead Integration Architect

People Operations Lead

Instructional Technology Lead

AI Applications & Data Analytics Lead

System Test Software Lead

Camera Image Sensor Digital Design Engineer Lead

Environmental Health and Safety (EHS) Lead

Lead Compliance Engineer

Verification & Validation Lead

Senior Technical Product Manager - Data Governance Technology Platform Lead

Core Software Services Lead

ASIC Chip Design Lead

Data Platform Security & Governance Leader

Software Integration Lead – 5G CORE

Lead Embedded SW Engineer, Hardware Emulation

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