Top 4525 Hardware engineer Jobs in Stanford Ca

Hardware Engineer, RTL
Normal Computing Corporation —Palo Alto, CA
- $200,000 - $285,000 a year
- Full-time
- Hybrid work
- Senior level
Hardware Engineer, RTL/PD
Normal Computing Corporation —Palo Alto, CA
- $200,000 - $285,000 a year
- Full-time
- Hybrid work
- Senior level
4d
Hardware Validation Engineer
Etched —San Jose, CA
- $150,000 - $275,000 a year
- Full-time
- Research
- Mid-level
- Master's degree
- Health insurance
- Dental insurance
Hardware Engineer
Cisco Systems —Milpitas, CA
- $122,000 - $222,400 a year
- Full-time
- Mid-level
- Master's degree
- Doctor of Philosophy
- Paid parental leave
- Paid holidays
Hardware Design Engineer
Tensordyne —Sunnyvale, CA
- Remote
- Bachelor of Science
- Manufacturing
- Senior level
Quick Apply
Hardware Engineer, FPGA
Normal Computing Corporation —Palo Alto, CA
- $200,000 - $280,000 a year
- Full-time
- Hybrid work
- C++
- Senior level
- Python
Camera & Photos - Hardware Operations Engineer
Apple —Cupertino, CA
- $175,500 - $311,700 a year
- Laboratory experience
- Mid-level
- Bachelor's degree
- Employee stock purchase plan
- Health insurance
Hardware Engineer
Western Digital —San Jose, CA
- $91,100 - $112,779 a year
- Urgently hiring
- Computer Science
- Mid-level
- Java
- Health savings account
- AD&D insurance
Quick Apply
3d
Staff Hardware Design Engineer
Tensordyne —Sunnyvale, CA
- Remote
- 7 years
- Bachelor of Science
- Manufacturing
Quick Apply
GNC Hardware Test Engineer
Xona Space Systems —Burlingame, CA
- $130,000 - $150,000 a year
- Full-time
- Software troubleshooting
- Bachelor of Science
- Mid-level
Hardware Test Engineer
Reliable Robotics Corporation —Mountain View, CA
- $118,000 - $170,000 a year
- Email
- Computer science
- Computer Science
- Schematics
- 401(k)
Associate Electrical Hardware Engineer
Rhoda AI —Mountain View, CA
- $120,000 - $150,000 a year
- Full-time
- Experience equivalent to degree accepted
- Electrical Engineering
- Communication skills
Hardware Engineer, PCB
Normal Computing Corporation —Palo Alto, CA
- $200,000 - $285,000 a year
- Full-time
- Hybrid work
- Research
- Senior level
Hardware Engineer
Google —Mountain View, CA
- $150,250 - $189,000 a year
- Full-time
- Hybrid work
- Computer Science
- Schematics
- Mid-level
7d
Hardware Engineer
Teradyne —San Jose, CA
- $122,500 - $196,000 a year
- 5 years
- Bachelor of Science
- Engineering
- Paid holidays
- Disability insurance
Hardware Testing and Manufacturing Engineer
Google —Mountain View, CA
- $144,000 - $209,000 a year
- Full-time
- Master's degree
- 8 years
- Analysis skills
Sr. Hardware Test Engineer
Reliable Robotics Corporation —Mountain View, CA
- $180,000 - $260,000 a year
- Email
- Computer science
- Computer Science
- 5 years
- 401(k)
Hardware Engineer
Quanta Manufacturing Nashville —Fremont, CA
- $88,000 - $132,000 a year
- Full-time
- Mid-level
- 3 years
- Analysis skills
Quick Apply
Optical Transceiver Engineer
Coherent Corp. —Fremont, CA
- $80,500 - $131,813 a year
- Overtime
- CAD
- Bachelor of Science
- Writing skills
Hardware System Engineer
PTEC Solutions Inc. —San Jose, CA
- $116,000 - $136,000 a year
- Full-time
- System design
- Doctor of Philosophy
- In-person
- Health insurance
- Dental insurance
Quick Apply
2d

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hardware engineer jobs near stanford ca

Hardware Engineer, RTL

Normal Computing Corporation
Palo Alto, CA

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Job Details

Full-time
$200,000 - $285,000 a year

Qualifications

Verification (System development task)
Tooling
AI tools proficiency
Electronics design
System design for system development
SoC
Digital circuit design
Design engineering
Open source contribution
Engineering functional testing
SystemVerilog
Senior level
Debugging

Full Job Description

About Normal Computing

Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. Conventional chips spend most of their energy forcing determinism onto physics; ours compute with it. Stochastic, in-memory, asynchronous: the result is 10-100× more AI inference per dollar, per watt.

We co-design the full stack: AI-native EDA systems in production with the world's largest semiconductor companies, and the advanced ASICs they make possible. Backed by $85M+ from the world's leading deep-tech investors and built by scientists, engineers, and operators from the labs that built modern computing.

Normal works as one team across New York, Silicon Valley, London, Copenhagen, and Seoul. We hire people who want the hardest version of their craft, across every discipline, at every seniority.

The Role

As an RTL Design Engineer at Normal, you will design and verify the digital logic at the heart of Normal's thermodynamic hardware. This work sits at the intersection of classical ASIC design, novel computing architectures, and a development environment where the hardware and the algorithms are built together, not in sequence.

You will own RTL from microarchitecture to tapeout: writing microarchitecture specifications, creating synthesizable SystemVerilog, working with design verification engineers fully test the design using conventional and formal methods, and working closely physical design to make sure the design meets area and timing constraints. Because Normal's chips are not standard accelerators, the RTL engineer here is closer to first-principles decisions than at a larger company. You will be shaping architecture, not just implementing it.

This is a role for an engineer who collaborates effectively across teams, including architecture, verification and physical design. The strongest candidates have taped out silicon, written RTL and helped close coverage, and are comfortable working in an environment where the specification is still being developed in parallel.

What You'll Own

RTL Design: Write and own synthesizable RTL in SystemVerilog across blocks ranging from datapath logic to control and memory interfaces.
Microarchitecture: Work with architecture to translate high-level specifications into implementable microarchitectures.
Verification: Work closely with the verification team to review verification plans, assist on debug, and become a partner in closing coverage.
Physical Design Collaboration: Collaborate with physical design on timing closure, floorplanning constraints, and DFT.
Design Reviews: Participate in design reviews and contribute to architecture decisions, not just implementation.
Tapeout & Bring-up: Support tapeout preparation, integration, and post-silicon bring-up as needed.

What Makes You a Great Fit

Hands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place-and-route
Experience in closing coverage to a high level
At least one tapeout in your background, from any node and any company size
Experience working on datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront
Strong debugging instincts across simulation, waveforms, and formal counterexamples
Ability to work directly with architects and physical designers without needing a large intermediary layer
Industry experience in ASIC or SoC design

Bonus Points

Experience at an AI chip company where design and verification were tightly coupled
Open-source RTL contributions to projects like Chipyard, OpenTitan, or CVA6
Familiarity with RISC-V or other open ISAs
Experience with AI-assisted RTL or EDA tooling in your design workflow
Exposure to physical design constraints, floorplanning, or timing-driven RTL development

Equal Employment Opportunity Statement

Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.

Accessibility Accommodations

Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at [email protected].

Privacy Notice

By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.

Compensation Range: $200K - $285K

Apply Now

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hardware engineer jobs in stanford ca

Hardware Engineer, RTL

Hardware Engineer, RTL/PD

Hardware Validation Engineer

Hardware Engineer

Hardware Design Engineer

Hardware Engineer, FPGA

Camera & Photos - Hardware Operations Engineer

Hardware Engineer

Staff Hardware Design Engineer

GNC Hardware Test Engineer

Hardware Test Engineer

Associate Electrical Hardware Engineer

Hardware Engineer, PCB

Hardware Engineer

Hardware Engineer

Hardware Testing and Manufacturing Engineer

Sr. Hardware Test Engineer

Hardware Engineer

Optical Transceiver Engineer

Hardware System Engineer

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