Top 1779 Architect/software development Jobs in Sunnyvale, Ca

R&D Engineering, Architect
Synopsys —Sunnyvale, CA
- $208,000 - $312,000 a year
- 11+ years
- Master's degree
- Presentation skills
3d
Software Development Engineer
Apple —Cupertino, CA
- $152,071 - $220,900 a year
- Full-time
- Computer science
- Computer Science
- System design
- Employee stock purchase plan
- Health insurance
8d
Software Development Engineer
Zoom —San Jose, CA
- $224,770 - $271,200 a year
- Full-time
- Hybrid work
- Mid-level
- 3 years
- Master's degree
Architect - FPGA Design, AXI/ UCIe Protocol
Synopsys —Sunnyvale, CA
- $208,000 - $312,000 a year
- 11+ years
- Master's degree
- Presentation skills
Staff Software Development Engineer (LLM)
Fortinet —Sunnyvale, CA
- $196,500 - $219,300 a year
- Full-time
- Azure
- System design
- Databases
- Paid holidays
- Disability insurance
Software Development Engineer - IoT
Xoriant —Santa Clara, CA
- Contract
- Computer Science
- Mid-level
- Bachelor's degree
Quick Apply
Software Architect
Cadence Design Systems —San Jose, CA
- $178,500 - $331,500 a year
- Full-time
- Computer Science
- 5 years
- Bachelor of Science
- Employee stock purchase plan
- Paid holidays
Staff Software Development Engineer
Adobe —San Jose, CA
- $208,300 - $301,600 a year
- Full-time
- Computer science
- Computer Science
- Bachelor of Science
Principal Applied Scientist, ML Codesign
Amazon.com Services LLC —Sunnyvale, CA
- $228,700 - $309,400 a year
- Full-time
- Computer science
- 8 years
- Fair chance
- AD&D insurance
- Health insurance
14d
Senior Technical Program Manager -Robotics
TMP Worldwide India Private Limited for ERS US —Mountain View, CA
- $110,000 - $168,000 a year
- Email
- Computer science
- Computer Science
- Engineering
- AD&D insurance
- Paid holidays
Quick Apply
Senior Director of Architecture (PCIe, Storage & Memory)
Everforth —San Jose, CA
- Full-time
- Windows
- US work authorization
- Fair chance
- Health savings account
- Employee stock purchase plan
7d
Senior Director of Architecture (PCIe, Storage & Memory)
Everforth —San Jose, CA
- Full-time
- Windows
- US work authorization
- Fair chance
- Health savings account
- Employee stock purchase plan
7d
Senior Director of Architecture (PCIe, Storage & Memory)
Everforth —San Jose, CA
- Full-time
- Windows
- US work authorization
- Fair chance
- Health savings account
- Employee stock purchase plan
7d
Senior Director of Architecture (PCIe, Storage & Memory)
Everforth —San Jose, CA
- Full-time
- Windows
- US work authorization
- Fair chance
- Health savings account
- Employee stock purchase plan
7d
Electrical Engineer - Power Distribution
Everforth —Santa Clara, CA
- Full-time
- System design
- Mid-level
- Analysis skills
- Profit sharing
- Health insurance
Quick Apply
7d
Director of Residential Construction
Marlin Home Solutions LLC —Fremont, CA
- $130,000 - $230,000 a year
- Full-time
- Computer literacy
- Residential
- Continuous improvement
- Paid holidays
- Paid time off
Quick Apply
12d
Director of Residential Construction
Marlin Home Solutions LLC —Pleasanton, CA
- $130,000 - $230,000 a year
- Full-time
- Computer literacy
- Residential
- Continuous improvement
- Paid holidays
- Paid time off
Quick Apply
12d
Director of Residential Construction
Marlin Home Solutions LLC —Hayward, CA
- $130,000 - $230,000 a year
- Full-time
- Computer literacy
- Residential
- Continuous improvement
- Paid holidays
- Paid time off
Quick Apply
12d
Platforms and Devices Silicon Engineer - SoC Front-End / RTL Design (multiple openings)
Google —Mountain View, CA
- $176,700 - $198,000 a year
- Full-time
- Hybrid work
- Computer Science
- Mid-level
- Office
7d
Software Security Architect
NVIDIA —Santa Clara, CA
- $224,000 - $356,500 a year
- Full-time
- 11+ years
- Analysis skills
- Bachelor's degree
14d

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architect/software development jobs near sunnyvale, ca

R&D Engineering, Architect

Synopsys -
Sunnyvale, CA

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Job Details

$208,000 - $312,000 a year
3 days ago

Qualifications

Engineering development testing
FPGA
Firmware
Firmware development
Production systems
Hardware support
FPGA circuit design
Logic analyzers
Hardware diagnostics
Debugging

Full Job Description

We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years deep in the world where real hardware meets pre-silicon design, and you know that the magic happens in the adapter layer, the piece that makes a DUT running at 10MHz talk convincingly to a PCIe Gen5 device expecting multi-gigabit speeds. You think in protocol state machines and FPGA resource budgets at the same time. You have debugged enough bring-up failures to know that the issue is almost never where it first appears, and you are the person who stays with the waveform until the actual root cause shows itself.

You are comfortable working across RTL, firmware, and board-level hardware without losing sight of what the customer is actually trying to validate. When a protocol spec says one thing and the real device does another, you figure out how to bridge that gap in a way that works in production, not just in simulation. You do not need a perfect requirements doc to start building. You talk to the IP team, the emulation team, and the customer, then you go build the thing that connects all three worlds.

At Synopsys, you will work on Speed Adapter solutions that enable the most advanced system-level validation in the industry. The protocols are cutting edge, the customers are the ones defining the next generation of silicon, and what you build will directly determine whether their chip works when it comes back from the fab.

What You'll Be Doing

Design and develop Speed Adapter solutions for PCIe Gen5/Gen6, CXL 2.0/3.x, UCIe, and AXI protocols that bridge real-world high-speed I/O with designs running on ZeBu emulation and HAPS prototyping platforms
Implement protocol logic and speed adaptation functionality on FPGA-based platforms, managing the translation layer between multi-gigabit real-world interfaces and reduced-speed DUTs
Develop and debug RTL, firmware, and system-level components across the full Speed Adapter stack, from transceiver configuration to protocol state machines to host integration
Collaborate with IP teams, emulation platform engineers, and prototyping teams to deliver integrated system-level validation solutions that customers can deploy in their labs
Build reference designs, example flows, and integration documentation that enable customers to connect their DUTs to real devices, testers, and hosts with minimal friction
Support customer escalations involving complex system-level issues, performing root-cause analysis across hardware, firmware, and protocol layers to deliver solutions that actually resolve the problem
Contribute to roadmap planning and feature definition for next-generation Speed Adapter products, including emerging protocols and differentiated capabilities not available from competitors

The Impact You Will Have

Enable top semiconductor and hyperscale customers to validate their next-generation SoCs against real-world devices months before silicon, reducing time-to-market and catching integration issues that simulation cannot find
Deliver Speed Adapter solutions that become the reference standard for In-Circuit Emulation and system-level validation workflows across the industry
Influence the adoption and implementation of emerging protocols like PCIe Gen7, CXL 4.0, and UCIe by building the tools that make early validation possible
Reduce customer bring-up time from weeks to days by delivering robust, well-documented adapter solutions that work out of the box
Shape the technical direction of Synopsys' hardware-assisted verification strategy, bridging IP, emulation, and prototyping into a unified system-level validation platform
Contribute to patent-pending technologies that differentiate Synopsys Speed Adapter solutions from competitive offerings and create measurable value for customers
Build the validation infrastructure that helps customers catch critical bugs in PCIe, CXL, and UCIe implementations before they become silicon respins

What You'll Need

12 years+ relevant experience
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent hands-on experience in digital design and FPGA-based systems
Deep hands-on experience with at least two of the following protocols: UCIe, PCIe (Gen4 or later), CXL (2.0 or later), or AXI, including implementation or validation work, not just integration
Strong RTL development skills and proven experience designing, debugging, and deploying logic on FPGA platforms in production or customer-facing environments
Experience with system-level validation, emulation, or prototyping environments where you have worked across the hardware/software boundary to bring up and debug complex systems
Solid understanding of high-speed serial interfaces, including transceiver configuration, link training, and physical layer bring-up
Demonstrated ability to debug across RTL, firmware, and board-level hardware, using tools like waveform viewers, logic analyzers, protocol analyzers, and embedded debuggers
Experience with ZeBu, HAPS, Veloce, Palladium, or similar emulation/prototyping platforms is a strong plus, as is familiarity with In-Circuit Emulation or Direct-ICE workflows

Who You Are

You can walk into a customer lab where nothing is working, pull waveforms, check register states, and narrow a system-level failure down to a specific protocol violation or timing issue within a few hours
You write RTL that other engineers can read and maintain, and you care about resource utilization, timing closure, and what happens when the design has to run on a different FPGA family next year
You are comfortable presenting a technical tradeoff to a senior architect or customer engineering team, explaining why approach A costs more FPGA resources but solves the real-world interoperability problem that approach B does not
You do not wait for someone else to define the integration plan. You talk to the IP team, the platform team, and the customer, then you write the plan and start building
You have worked on at least one project where the protocol spec was still evolving, the hardware was not quite ready, and you had to build something that worked anyway
You treat customer escalations as opportunities to understand the real problem, not just close the ticket, and you follow through until the solution is validated in the customer's environment

The Team You'll Be Part Of

You will join the Speed Adapter engineering team within the Hardware-Assisted Verification (TPG-HAV) organization, reporting to Cheng-yun Chen. This team builds the critical bridge between Synopsys' ZeBu emulation and HAPS prototyping platforms and the real-world devices, testers, and hosts that customers need to connect to their pre-silicon designs. The team works closely with IP teams developing PCIe, CXL, UCIe, and other high-speed protocols, as well as with emulation and prototyping platform engineers to deliver integrated system-level validation solutions. You will be part of a global team of engineers who are defining the next generation of In-Circuit Emulation and system-level validation technology, working on protocols and use cases that are not yet in production anywhere else in the industry.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

#TPG

Apply Now

Refine Your Search

architect/software development jobs in sunnyvale, ca

R&D Engineering, Architect

Software Development Engineer

Software Development Engineer

Architect - FPGA Design, AXI/ UCIe Protocol

Staff Software Development Engineer (LLM)

Software Development Engineer - IoT

Software Architect

Staff Software Development Engineer

Principal Applied Scientist, ML Codesign

Senior Technical Program Manager -Robotics

Senior Director of Architecture (PCIe, Storage & Memory)

Senior Director of Architecture (PCIe, Storage & Memory)

Senior Director of Architecture (PCIe, Storage & Memory)

Senior Director of Architecture (PCIe, Storage & Memory)

Electrical Engineer - Power Distribution

Director of Residential Construction

Director of Residential Construction

Director of Residential Construction

Platforms and Devices Silicon Engineer - SoC Front-End / RTL Design (multiple openings)

Software Security Architect

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