Top 1196 Hardware architect Jobs in Fremont, Ca

ASIC DFT Emulation Technical Lead
Cisco Systems —San Jose, CA
- $166,300 - $307,800 a year
- Full-time
- 3 years
- Master's degree
- Bachelor's degree
- Paid parental leave
- Paid holidays
Business Development Manager
Gatco Inc. —San Leandro, CA
- $85,000 - $95,000 a year
- Full-time
- Hospitality
- Mid-level
- Residential
- Health insurance
- Dental insurance
Quick Apply
3d
Systems Architect - High-Speed Compute Hardware Engineering Technical Leader (Hybrid)
Cisco Systems —San Jose, CA
- $151,300 - $250,900 a year
- Full-time
- Hybrid work
- System design
- Office
- Analysis skills
- Paid parental leave
- Paid holidays
Commercial Project Manager/Estimator - Doors Frames Hardware (Experience Required)
Magnum Drywall Inc —San Jose, CA
- $120,000 - $160,000 a year
- Full-time
- Background check
- 5 years
- US work authorization
- Relocation assistance
- Health insurance
Quick Apply
5d
Sr. Principal Hardware Architect for Optical Transceivers
Coherent Corp. —Fremont, CA
- Full-time
- Bachelor of Science
- Office
- Analysis skills
Senior ASIC Design Verification Engineer
Cisco Systems —San Jose, CA
- $149,100 - $282,000 a year
- Full-time
- Master's degree
- Doctor of Philosophy
- US work authorization
- Paid parental leave
- Paid holidays
ASIC Engineering Technical Leader (onsite) - 2014979
Cisco Systems —San Jose, CA
- $151,300 - $281,800 a year
- Full-time
- Hybrid work
- Computer Science
- System design
- Research
- Paid parental leave
- Paid holidays
Architect/Project Manager
West Coast Architectural Millwork —Redwood City, CA
- $120,000 - $140,000 a year
- 8 hour shift
- AutoCAD
- Construction site
- Mid-level
- Health insurance
- 401(k)
Quick Apply
Senior mixed-signal electrical engineer (Board Level)
ASML —San Jose, CA
- $165,375 - $275,625 a year
- Full-time
- Microsoft Excel
- 5 years
- Doctor of Philosophy
- Paid holidays
- Health insurance
Senior Staff Data Center Operations Engineer, GPU Hardware Architecture
Crusoe —Sunnyvale, CA
- $179,000 - $218,000 a year
- Full-time
- Bachelor of Science
- Analysis skills
- Training & development
- Commuter assistance
- Paid parental leave
Quick Apply
Software Project Manager II - Foundation
ASML —San Jose, CA
- $149,625 - $224,438 a year
- Full-time
- Hybrid work
- 5 years
- Senior level
- Paid holidays
- Health insurance
Mechanical Engineering Technical Leader
Cisco Systems —San Jose, CA
- $151,300 - $250,900 a year
- Full-time
- 3 years
- Master's degree
- Analysis skills
- Paid parental leave
- Paid holidays
Senior Technical Program Manager -Robotics
TMP Worldwide India Private Limited for ERS US —Mountain View, CA
- $110,000 - $168,000 a year
- Email
- Computer science
- Computer Science
- Engineering
- AD&D insurance
- Paid holidays
Quick Apply
Principal Software Engineer, Endpoint AI Framework (Hybrid)
CrowdStrike —Sunnyvale, CA
- $229,000 - $412,000 a year
- Hybrid work
- Office
- Windows
- Linux
- Paid holidays
- Health insurance
7d
ASIC Design Verification Engineer
Cisco Systems —San Jose, CA
- $138,100 - $256,000 a year
- Full-time
- Master's degree
- Bachelor's degree
- Doctor of Philosophy
- Paid parental leave
- Paid holidays
Project Manager I - Doors Frames and Hardware
ISEC —Pleasanton, CA
- $110,682 - $139,707 a year
- Full-time
- Construction site
- Mid-level
- Bachelor's degree
Quick Apply
Hardware Engineer - System Board Design (PCB) (Onsite)
Cisco Systems —Milpitas, CA
- $124,000 - $226,000 a year
- Full-time
- Master's degree
- Doctor of Philosophy
- US work authorization
- Paid parental leave
- Paid holidays
Project Manager I - Doors Frames and Hardware
ISEC —Pleasanton, CA
- $110,682 - $139,707 a year
- Full-time
- Construction site
- Mid-level
- Bachelor's degree
Quick Apply
Senior Principal Power Engineer
Manpower Engineering —San Jose, CA
- Full-time
- Remote
- Senior level
- Leadership
- Communication skills
- Health savings account
- Disability insurance
Quick Apply
Hardware Engineer, Architect
Normal Computing Corporation —Palo Alto, CA
- Full-time
- Hybrid work
- Computer science
- Computer Science
- C++

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ASIC DFT Emulation Technical Lead

Cisco Systems -
San Jose, CA

Apply Now

Job Details

Full-time
$166,300 - $307,800 a year

Benefits

Paid parental leave
Paid holidays
Disability insurance
Health insurance
Dental insurance
401(k)
RSU
Parental leave
Vision insurance
401(k) matching
Life insurance

Qualifications

Verilog
Debugging

Full Job Description

The application window is expected to close on: 10/20/2026Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

Meet The Team

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.

Your Impact

As an ASIC DFT - Emulation Technical Lead, you will play a critical role in driving the DFT emulation strategy for Silicon One. You’ll architect state-of-the-art emulation environments, lead pre-silicon test plan execution, and validate complex scan, MBIST, and JTAG architectures on platforms like Palladium, Veloce, or Zebu. Partnering closely with front-end RTL, physical design, and ATPG teams, you will troubleshoot critical issues and ensure high-quality post-silicon pattern conversion. Your technical leadership and cross-functional collaboration will guarantee seamless silicon bring-up and optimal test coverage across next-generation hardware platforms.

Minimum Qualifications

Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience
Prior emulation experience on platforms such as Palladium, Veloce, or Zebu as well as experience with compilation and debug.
Prior experience with Verilog and System Verilog.
Prior experience with C/C++ and scripting skills with Tcl or Python/Perl.

Preferred Qualifications

Prior experience defining DFT Emulation strategy.
Prior experience with JTAG protocol, scan architecture, MBIST and boundary scan.
UVM and advanced System Verilog knowledge.
Post Silicon validation and/or debugging experience.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $186,900.00 to $267,700.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:

10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:

.75% of incentive target for each 1% of revenue attainment up to 50% of quota;
1.5% of incentive target for each 1% of attainment between 50% and 75%;
1% of incentive target for each 1% of attainment between 75% and 100%; and
Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area:
$186,900.00 - $307,800.00

Non-Metro New York state& Washington state:
$166,300.00 - $274,100.00

For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.

** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

Apply Now

Refine Your Search

hardware architect jobs in fremont, ca

ASIC DFT Emulation Technical Lead

Business Development Manager

Systems Architect - High-Speed Compute Hardware Engineering Technical Leader (Hybrid)

Commercial Project Manager/Estimator - Doors Frames Hardware (Experience Required)

Sr. Principal Hardware Architect for Optical Transceivers

Senior ASIC Design Verification Engineer

ASIC Engineering Technical Leader (onsite) - 2014979

Architect/Project Manager

Senior mixed-signal electrical engineer (Board Level)

Senior Staff Data Center Operations Engineer, GPU Hardware Architecture

Software Project Manager II - Foundation

Mechanical Engineering Technical Leader

Senior Technical Program Manager -Robotics

Principal Software Engineer, Endpoint AI Framework (Hybrid)

ASIC Design Verification Engineer

Project Manager I - Doors Frames and Hardware

Hardware Engineer - System Board Design (PCB) (Onsite)

Project Manager I - Doors Frames and Hardware

Senior Principal Power Engineer

Hardware Engineer, Architect

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