Top 2734 Electrical engineer Jobs in Union City, Ca

ASIC Synthesis, STA Engineer
Axonne Inc. —San Jose, CA
- $110,000 - $175,000 a year
- Full-time
- 5 years
- Master's degree
- Analysis skills
- Health savings account
- Health insurance
Quick Apply
1d
Electrical Engineer (Utility/Smart Grid)
IND Technology —Burlingame, CA
- $120,000 - $130,000 a year
- Full-time
- Mid-level
- 3 years
- Master's degree
- Health insurance
- Dental insurance
Quick Apply
7d
Electrical Engineer
RK Electric —Fremont, CA
- $80,000 - $125,000 a year
- Full-time
- Background check
- 5 years
- System design
- Health savings account
- Paid holidays
Quick Apply
Design Engineer - Electrical/Electronics EE (non-software) Background
Electronics Manufacturing Company —Campbell, CA
- $130,000 - $140,000 a year
- Full-time
- 5 years
- Bachelor of Science
- Microsoft Office
- Paid holidays
- Health insurance
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Member of Technical Staff - Switch Systems Test Engineer
Coherent Corp. —Fremont, CA
- Overtime
- 7 years
- Bachelor of Science
- Office
Electrical Engineer
Abbott Laboratories —Sunnyvale, CA
- $73,900 - $116,000 a year
- Full-time
- Mid-level
- Electrical Engineering
6d
Electrical Engineer
Mizuho OSI —Union City, CA
- $82,000 - $150,000 a year
- Background check
- Microsoft Excel
- Microsoft Outlook
- Health insurance
- Dental insurance
Electrical Design Engineer
Charge Robotics —San Leandro, CA
- $165,000 - $220,000 a year
- Full-time
- System design
- Mid-level
- Office
14d
Electrical Engineer I
Zettaone Technologies —Fremont, CA
- Email
- Software troubleshooting
- Mid-level
- Office
Component Engineer
Apple —Cupertino, CA
- $123,739 - $218,000 a year
- Research
- Mid-level
- 1 year
- Employee stock purchase plan
- Health insurance
Product Engineer
Inneos —Pleasanton, CA
- $90,000 - $110,000 a year
- Full-time
- Bachelor of Science
- Mid-level
- 3 years
- Health insurance
- Dental insurance
Quick Apply
10d
Principal Electrical Engineer
PG&E Corporation —Danville, CA
- $155,000 - $265,000 a year
- Engineering
- Mentoring
- Senior level
Electrical Engineer
Therm-x of California —Hayward, CA
- $85,000 - $95,000 a year
- Full-time
- Microsoft Outlook
- Bachelor of Science
- Mid-level
Quick Apply
Senior Electrical Engineer
PG&E Corporation —Danville, CA
- $122,000 - $194,000 a year
- 5 years
- Engineering
- Data analysis skills
ATS Engineer
PG&E Corporation —Danville, CA
- $109,000 - $175,000 a year
- Engineering
- Data analysis skills
- Laboratory experience
Senior Electrical Engineer
TechniPower, Inc. —Santa Clara, CA
- $120,000 - $160,000 a year
- 8 years
- In-person
- Senior level
Quick Apply
Electrical Engineer
On-Board Companies —Sunnyvale, CA
- $63 - $74 an hour
- Email
- Construction site
- Analysis skills
- US work authorization
- Health insurance
- Dental insurance
Quick Apply
Facilities Electrical Engineer
Oxford Global Resources —San Jose, CA
- $113,000 - $170,000 a year
- AutoCAD
- Bachelor of Science
- System design
- Health insurance
- Dental insurance
Quick Apply
Electrical Design Engineer Level 2 / 3
Northrop Grumman —Sunnyvale, CA
- $91,800 - $171,000 a year
- Overtime
- Mid-level
- Master's degree
- Travel
- Paid holidays
- Disability insurance
Failure Analysis Engineer
HYVE Solutions —Fremont, CA
- $142,000 - $169,000 a year
- Full-time
- Background check
- 3 years
- Analysis skills
- Health savings account
- Paid holidays
Quick Apply
7d

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electrical engineer jobs near union city, ca

ASIC Synthesis, STA Engineer

Axonne Inc.
San Jose, CA

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Job Details

Full-time
$110,000 - $175,000 a year
1 day ago

Benefits

Health savings account
Health insurance
401(k)
Flexible spending account
Paid time off
Life insurance

Qualifications

Automation
Tooling
Process design
Semiconductor electronics
Master's degree
Bachelor's degree in engineering
Digital circuit design
Bachelor's degree
Computer Engineering
Electrical Engineering
Cross-functional collaboration
Cross-functional communication

Full Job Description

Company Overview:

Axonne Inc. is an innovative fabless Silicon Valley semiconductor design company specializing in the development of cutting-edge high-speed networking solutions for the automotive and robotics industries. With a focus on driving digital transformation, Axonne combines advanced research with practical applications to create products that enhance connectivity, data transfer, security, and system integration, facilitating the realization of artificial intelligence and machine learning. Axonne continues to be a trusted partner for organizations seeking to future-proof their value proposition and unlock new possibilities and opportunities for growth and success.

About the Role

We are looking for an experienced Front-End Design Engineer to own the RTL-to-gates flow for our ASIC/SoC designs. The ideal candidate will be a strong hands-on synthesis and static timing analysis (STA) expert. who can also implement scan insertion (DFT) and memory BIST insertion, and stitch these steps into a clean, repeatable, sign-off-quality flow. This role sits between RTL design and physical implementation — you will hand off a clean, timing-constrained, DFT-ready gate-level netlist to the backend physical design team and work closely with them through timing closure. Backend place-and-route is not part of this role.

Responsibilities

Own logic synthesis of RTL designs to gate-level netlists, driving timing, area, and power closure
Develop, own, and maintain SDC constraints across modes/corners; debug and resolve synthesis-stage timing violations (setup/hold, clock domain crossings, false/multicycle paths)
Build and maintain the synthesis and DFT flow — scripting, tool integration, and methodology — rather than just running an existing one
Work directly with backend physical design engineers to align constraints, handoff netlists, and resolve timing or DFT-related issues that surface during P&R
Implement scan chain insertion (scan stitching, chain balancing, lockup latches) and run ATPG to generate and grade test patterns
Insert and configure memory BIST (MBIST) IP for embedded memories (SRAM/ROM/register files), including controller integration and memory grouping
Debug DFT-related issues surfaced during ATPG, simulation, or silicon bring-up (e.g., scan test failures, BIST diagnostics)
Generate and review test coverage reports (stuck-at, transition) and drive coverage closure
Maintain flow documentation and drive automation improvements

Required Qualifications

Bachelor's or Master's degree in Electrical/Computer Engineering or related field
5+ years of hands-on experience in ASIC front-end flows, with strong depth in synthesis and STA
Proficiency with industry-standard synthesis tools (e.g., Synopsys Design Compiler / Fusion Compiler, Cadence Genus) and STA tools (e.g., Synopsys PrimeTime)
Demonstrated ability to construct and own a synthesis/DFT flow from scratch, not just execute an established one
Strong command of SDC constraints, timing exceptions, and multi-corner/multi-mode analysis
Direct experience implementing memory BIST insertion (e.g., Siemens Tessent MemoryBIST, Synopsys STAR Memory System)
Strong scripting ability (Tcl, Python, or Perl) for flow automation
Comfortable working cross-functionally with physical design engineers on constraint and timing handoff issues

Nice to Have

Hands-on experience with scan insertion and ATPG tools (e.g., Synopsys DFTMAX/TetraMAX, Siemens Tessent Scan/FastScan, Cadence Modus), including pattern generation and grading
Experience with logic equivalence checking (LEC) tools (e.g., Synopsys Formality, Cadence Conformal)
Familiarity with ATE test program development or working with test engineering teams

Pay: $110,000.00 - $175,000.00 per year

Benefits:

401(k)
Flexible spending account
Health insurance
Health savings account
Life insurance
Paid time off

Education:

Bachelor's (Required)

Experience:

Logic Synthesis, STA : 5 years (Required)

Ability to Relocate:

San Jose, CA 95110: Relocate before starting work (Required)

Work Location: In person

Quick Apply

Refine Your Search

electrical engineer jobs in union city, ca

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