Top 1342 Asic design engineer Jobs

Lead ASIC DFT Engineer
Cyient —San Jose, CA
- $80 - $85 an hour
- Full-time
- Analysis skills
- Mentoring
- In-person
Quick Apply
Advanced ASIC FPGA Verification Engineer for Crypto and Cross Domain Solutions
General Dynamics Mission Systems, Inc —Scottsdale, AZ
- $135,396 - $150,205 a year
- Full-time
- 3 years
- Master's degree
- Analysis skills
Principal Engineer - FPGA/ASIC Design
Rolls-Royce —Indianapolis, IN
- $113,179 - $183,916 a year
- Full-time
- Hybrid work
- Office
- Windows
- 3 years
- Paid parental leave
- Health savings account
5d
Circuit Design Engineer
United Premier —El Segundo, CA
- $80 an hour
- Full-time
- Master's degree
- 8 years
- Analysis skills
- Flexible schedule
Quick Apply
12d
Electronics Engineer / Senior Electronics Engineer
Mitutoyo Research & Development America, Inc. —Kirkland, WA
- $80,000 - $150,000 a year
- Full-time
- Hybrid work
- US work authorization
- In-person
- Senior level
- Paid holidays
- Disability insurance
4d
ASIC Design Verification Engineer
Positron AI —Remote
- $200,000 - $350,000 a year
- Full-time
- Remote
- Master's degree
- 8 years
- Analysis skills
Quick Apply
ASIC Digital Design, Staff Engineer -18138
Synopsys —Boxborough, MA
- $114,000 - $170,000 a year
- 5 years
- Data analysis skills
- Master's degree
ASIC Digital Design, Staff Engineer
Synopsys —Boxborough, MA
- $114,000 - $170,000 a year
- 5 years
- Data analysis skills
- Master's degree
ASIC Digital Design, Sr Staff Engineer
Synopsys —Boxborough, MA
- $138,000 - $208,000 a year
- Data analysis skills
- Master's degree
- Analysis skills
ASIC Physical Design Engineer, Principal
Positron AI —Remote
- $150,000 - $300,000 a year
- Full-time
- Remote
- 11+ years
- US work authorization
- Senior level
- Paid holidays
- Disability insurance
Quick Apply
4d
ASIC RTL Design Engineer
Oxford Global Resources —Burlingame, CA
- $83 - $93 an hour
- Full-time
- Hybrid work
- In-person
- Senior level
- Health insurance
- Dental insurance
Quick Apply
Asic Engineer
Actalent —Broomfield, CO
- $140,000 - $240,000 a year
- Full-time
- Engineering
- Office
- 3 years
- Employee stock purchase plan
- Paid holidays
Quick Apply
3d
ASIC Verification Engineer (Python/Cocotb)
Oxford Global Resources —Burlingame, CA
- $80 - $90 an hour
- Full-time
- Hybrid work
- In-person
- Senior level
- Python
- Health insurance
- Dental insurance
Quick Apply
Digital Design Engineer - Level 5 - Linthicum
Northrop Grumman —Linthicum Heights, MD
- $185,900 - $278,900 a year
- Overtime
- Computer science
- 7 years
- Computer Science
- Paid holidays
- Disability insurance
ASIC Design Engineer
Sivaltech —Milpitas, CA
- Mid-level
- Bachelor's degree
Design Verification Engineer - SoC
Etched —San Jose, CA
- $150,000 - $275,000 a year
- Full-time
- Mid-level
- Office
- Analysis skills
- Health insurance
- Dental insurance
RTL Design Engineer
Etched —San Jose, CA
- $150,000 - $275,000 a year
- Full-time
- 5 years
- Office
- Senior level
- Health insurance
- Dental insurance
ASIC Logic Design Engineer (Remote)
ASIC North, Inc. —Remote
- $120,000 - $165,000 a year
- Full-time
- Remote
- Bachelor of Science
- Analysis skills
- Travel
- Wellness program
- Health savings account
2d
ASIC RTL Design Engineer, Ethernet IP & SoC Integration, AI Hardware
Tesla —Palo Alto, CA
- $128,000 - $312,000 a year
- Full-time
- 3 years
- Senior level
- Electrical Engineering
- Commuter assistance
- Health savings account
Senior Staff Engineer, ASIC Design/Implementation -- LEC/STA/Power Analysis
Marvell —Irvine, CA
- $135,900 - $201,130 a year
- Full-time
- Computer Science
- 5 years
- Master's degree
- Employee stock purchase plan

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Lead ASIC DFT Engineer

Cyient -
San Jose, CA

Quick Apply

Job Details

Full-time | Contract
$80 - $85 an hour

Qualifications

Analog circuit design
Engineering development testing
Electronics functional testing
Integrated circuits (ICs)
Ramps
Analysis skills
SoC
System architecture design
Simulation tools
Root cause analysis
Test analysis
Python
Debugging
Cross-functional communication

Full Job Description

Title - Lead ASIC DFT Engineer

Location – San Jose, CA.

Duration - Contract

Job Description

Experience

10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Key Responsibilities

Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
Act as a technical escalation point for advanced DFT and post-silicon debug issues.
Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

Required Skills & Qualifications

Strong hands-on experience in ASIC DFT with end-to-end ownership.
Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
Experience with MBIST implementation and verification; SMS experience preferred.
Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
Proven post-silicon debug and silicon bring-up experience.
Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
Strong communication skills and the ability to work independently with minimal ramp-up.

Preferred Experience

MBIST post-silicon validation.
ATPG simulations and fault coverage debug.
DFT RTL, DFD, DFT verification, and IP-level DFT integration.
DFT SDC creation and DFT timing closure support.
Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
TCL/PERL scripting for DFT automation, reporting, and debug.
Experience working across multiple ASIC technology nodes and complex product development cycles.
Familiarity with yield learning, diagnosis, and manufacturing test optimization.

Pay: $80.00 - $85.00 per hour

Work Location: In person

Quick Apply

Refine Your Search

asic design engineer jobs

Lead ASIC DFT Engineer

Advanced ASIC FPGA Verification Engineer for Crypto and Cross Domain Solutions

Principal Engineer - FPGA/ASIC Design

Circuit Design Engineer

Electronics Engineer / Senior Electronics Engineer

ASIC Design Verification Engineer

ASIC Digital Design, Staff Engineer -18138

ASIC Digital Design, Staff Engineer

ASIC Digital Design, Sr Staff Engineer

ASIC Physical Design Engineer, Principal

ASIC RTL Design Engineer

Asic Engineer

ASIC Verification Engineer (Python/Cocotb)

Digital Design Engineer - Level 5 - Linthicum

ASIC Design Engineer

Design Verification Engineer - SoC

RTL Design Engineer

ASIC Logic Design Engineer (Remote)

ASIC RTL Design Engineer, Ethernet IP & SoC Integration, AI Hardware

Senior Staff Engineer, ASIC Design/Implementation -- LEC/STA/Power Analysis

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